Shuuichirou Ishii e31c70ac04 target-arm: Add support for Fujitsu A64FX ... Add a definition for the Fujitsu A64FX processor. The A64FX processor does not implement the AArch32 Execution state, so there are no associated AArch32 Identification registers. For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths. The Identification register values are defined based on the FX700, and have been tested and confirmed. Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-09-01 11:08:18 +01:00
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a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c	target-arm: Add support for Fujitsu A64FX	2021-09-01 11:08:18 +01:00
cpu_tcg.c	target/arm: Enable MVE in Cortex-M55	2021-09-01 11:08:18 +01:00
cpu-param.h
cpu-qom.h
cpu.c	target/arm: Avoid assertion trying to use KVM and multiple ASes	2021-08-26 17:02:01 +01:00
cpu.h	target/arm: Do hflags rebuild in cpsr_write()	2021-08-26 17:02:01 +01:00
crypto_helper.c
debug_helper.c	accel/tcg: Remove TranslatorOps.breakpoint_check	2021-07-21 07:47:05 -10:00
gdbstub64.c
gdbstub.c	target/arm: Enforce that M-profile SP low 2 bits are always zero	2021-07-27 10:57:39 +01:00
helper-a64.c	tcg: Rename helper_atomic_*_mmu and provide for user-only	2021-07-21 07:45:38 -10:00
helper-a64.h
helper-mve.h	target/arm: Implement MVE VRINT insns	2021-09-01 11:08:17 +01:00
helper-sve.h
helper.c	target/arm: Do hflags rebuild in cpsr_write()	2021-08-26 17:02:01 +01:00
helper.h	target/arm: Implement HSTR.TJDBX	2021-08-26 17:02:01 +01:00
idau.h
internals.h	target/arm: Export aarch64_sve_zcr_get_valid_len	2021-07-27 10:57:40 +01:00
iwmmxt_helper.c
Kconfig
kvm64.c	target/arm/kvm64: Ensure sve vls map is completely clear	2021-08-26 17:01:59 +01:00
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c	target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()	2021-08-25 10:48:50 +01:00
m_helper.c	target/arm: Implement M-profile trapping on division by zero	2021-08-25 10:48:50 +01:00
m-nocp.decode
machine.c
meson.build
monitor.c
mte_helper.c
mve_helper.c	target/arm: Implement MVE VRINT insns	2021-09-01 11:08:17 +01:00
mve.decode	target/arm: Implement MVE VRINT insns	2021-09-01 11:08:17 +01:00
neon_helper.c
neon-dp.decode
neon-ls.decode	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
neon-shared.decode	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
op_addsub.h
op_helper.c	target/arm: Implement HSTR.TJDBX	2021-08-26 17:02:01 +01:00
pauth_helper.c
psci.c
sve_helper.c
sve.decode	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
syndrome.h	target/arm: Implement HSTR.TJDBX	2021-08-26 17:02:01 +01:00
t16.decode
t32.decode	target/arm: Implement MVE VCTP	2021-08-25 10:48:50 +01:00
tlb_helper.c
trace-events
trace.h
translate-a32.h	target/arm: Implement MVE VCTP	2021-08-25 10:48:50 +01:00
translate-a64.c	accel/tcg: Remove TranslatorOps.breakpoint_check	2021-07-21 07:47:05 -10:00
translate-a64.h
translate-m-nocp.c
translate-mve.c	target/arm: Implement MVE VRINT insns	2021-09-01 11:08:17 +01:00
translate-neon.c	target/arm: Implement MVE VADD (floating-point)	2021-09-01 11:08:16 +01:00
translate-sve.c	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
translate-vfp.c	target/arm: Implement MVE VMOV to/from 2 general-purpose registers	2021-08-25 10:48:50 +01:00
translate.c	target/arm: Implement HSTR.TJDBX	2021-08-26 17:02:01 +01:00
translate.h	target/arm: Implement MVE VADD (floating-point)	2021-09-01 11:08:16 +01:00
vec_helper.c	target/arm: Implement MVE VMULL (polynomial)	2021-08-25 10:48:49 +01:00
vec_internal.h	target/arm: Implement MVE VMULL (polynomial)	2021-08-25 10:48:49 +01:00
vfp_helper.c
vfp-uncond.decode
vfp.decode