05def917e1
Only a few important registers are added, especially the SRAM_VER register. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/*
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* Allwinner SRAM controller emulation
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*
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* Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_MISC_ALLWINNER_SRAMC_H
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#define HW_MISC_ALLWINNER_SRAMC_H
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#include "qom/object.h"
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#include "hw/sysbus.h"
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#include "qemu/uuid.h"
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/**
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* Object model
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* @{
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*/
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#define TYPE_AW_SRAMC "allwinner-sramc"
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#define TYPE_AW_SRAMC_SUN8I_R40 TYPE_AW_SRAMC "-sun8i-r40"
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OBJECT_DECLARE_TYPE(AwSRAMCState, AwSRAMCClass, AW_SRAMC)
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/** @} */
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/**
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* Allwinner SRAMC object instance state
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*/
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struct AwSRAMCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/** Maps I/O registers in physical memory */
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MemoryRegion iomem;
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/* registers */
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uint32_t sram_ctl1;
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uint32_t sram_ver;
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uint32_t sram_soft_entry_reg0;
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};
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/**
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* Allwinner SRAM Controller class-level struct.
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*
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* This struct is filled by each sunxi device specific code
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* such that the generic code can use this struct to support
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* all devices.
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*/
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struct AwSRAMCClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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uint32_t sram_version_code;
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};
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#endif /* HW_MISC_ALLWINNER_SRAMC_H */
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