386e29554e
Move the NCPU definition to arm_gic.c: the maximum number of CPU interfaces is defined by the GIC architecture specification to be 8, so we don't need to have this #define in each of the sources files which currently includes arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
/*
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* Cortex-A15MPCore internal peripheral emulation.
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*
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* Copyright (c) 2012 Linaro Limited.
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* Written by Peter Maydell.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysbus.h"
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/* Configuration for arm_gic.c:
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* how to ID current CPU
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*/
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static inline int gic_get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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#include "arm_gic.c"
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/* A15MP private memory region. */
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typedef struct A15MPPrivState {
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gic_state gic;
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uint32_t num_cpu;
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uint32_t num_irq;
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MemoryRegion container;
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} A15MPPrivState;
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static int a15mp_priv_init(SysBusDevice *dev)
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{
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A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev);
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gic_init(&s->gic, s->num_cpu, s->num_irq);
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/* Memory map (addresses are offsets from PERIPHBASE):
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* 0x0000-0x0fff -- reserved
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* 0x1000-0x1fff -- GIC Distributor
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* 0x2000-0x2fff -- GIC CPU interface
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* 0x4000-0x4fff -- GIC virtual interface control (not modelled)
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* 0x5000-0x5fff -- GIC virtual interface control (not modelled)
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* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
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*/
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memory_region_init(&s->container, "a15mp-priv-container", 0x8000);
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memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
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memory_region_add_subregion(&s->container, 0x2000, &s->gic.cpuiomem[0]);
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sysbus_init_mmio(dev, &s->container);
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return 0;
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}
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static Property a15mp_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
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/* The Cortex-A15MP may have anything from 0 to 224 external interrupt
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* IRQ lines (with another 32 internal). We default to 64+32, which
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* is the number provided by the Cortex-A15MP test chip in the
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* Versatile Express A15 development board.
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* Other boards may differ and should set this property appropriately.
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*/
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DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void a15mp_priv_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = a15mp_priv_init;
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dc->props = a15mp_priv_properties;
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/* We currently have no savable state outside the common GIC state */
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}
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static TypeInfo a15mp_priv_info = {
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.name = "a15mpcore_priv",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(A15MPPrivState),
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.class_init = a15mp_priv_class_init,
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};
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static void a15mp_register_types(void)
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{
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type_register_static(&a15mp_priv_info);
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}
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type_init(a15mp_register_types)
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