6390eed45c
Add the framework for decoding MVE insns, with the necessary new files and the meson.build rules, but no actual content yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614151007.4545-11-peter.maydell@linaro.org
147 lines
5.3 KiB
C
147 lines
5.3 KiB
C
/*
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* AArch32 translation, common definitions.
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*
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* Copyright (c) 2021 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_ARM_TRANSLATE_A64_H
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#define TARGET_ARM_TRANSLATE_A64_H
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/* Prototypes for autogenerated disassembler functions */
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bool disas_m_nocp(DisasContext *dc, uint32_t insn);
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bool disas_mve(DisasContext *dc, uint32_t insn);
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bool disas_vfp(DisasContext *s, uint32_t insn);
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bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
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bool disas_neon_dp(DisasContext *s, uint32_t insn);
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bool disas_neon_ls(DisasContext *s, uint32_t insn);
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bool disas_neon_shared(DisasContext *s, uint32_t insn);
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void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
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void arm_gen_condlabel(DisasContext *s);
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bool vfp_access_check(DisasContext *s);
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void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
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void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
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void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
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void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
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TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
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void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
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void gen_set_condexec(DisasContext *s);
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void gen_set_pc_im(DisasContext *s, target_ulong val);
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void gen_lookup_tb(DisasContext *s);
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long vfp_reg_offset(bool dp, unsigned reg);
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long neon_full_reg_offset(unsigned reg);
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long neon_element_offset(int reg, int element, MemOp memop);
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void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
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void clear_eci_state(DisasContext *s);
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static inline TCGv_i32 load_cpu_offset(int offset)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_ld_i32(tmp, cpu_env, offset);
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return tmp;
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}
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#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
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static inline void store_cpu_offset(TCGv_i32 var, int offset)
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{
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tcg_gen_st_i32(var, cpu_env, offset);
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tcg_temp_free_i32(var);
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}
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#define store_cpu_field(var, name) \
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store_cpu_offset(var, offsetof(CPUARMState, name))
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/* Create a new temporary and set it to the value of a CPU register. */
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static inline TCGv_i32 load_reg(DisasContext *s, int reg)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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load_reg_var(s, tmp, reg);
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return tmp;
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}
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void store_reg(DisasContext *s, int reg, TCGv_i32 var);
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void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, MemOp opc);
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void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, MemOp opc);
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void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc);
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void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc);
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#define DO_GEN_LD(SUFF, OPC) \
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static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_ld_i32(s, val, a32, index, OPC); \
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}
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#define DO_GEN_ST(SUFF, OPC) \
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static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_st_i32(s, val, a32, index, OPC); \
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}
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static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index)
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{
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gen_aa32_ld_i64(s, val, a32, index, MO_Q);
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}
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static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index)
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{
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gen_aa32_st_i64(s, val, a32, index, MO_Q);
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}
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DO_GEN_LD(8u, MO_UB)
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DO_GEN_LD(16u, MO_UW)
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DO_GEN_LD(32u, MO_UL)
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DO_GEN_ST(8, MO_UB)
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DO_GEN_ST(16, MO_UW)
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DO_GEN_ST(32, MO_UL)
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#undef DO_GEN_LD
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#undef DO_GEN_ST
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#if defined(CONFIG_USER_ONLY)
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#define IS_USER(s) 1
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#else
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#define IS_USER(s) (s->user)
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#endif
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/* Set NZCV flags from the high 4 bits of var. */
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#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
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/* Swap low and high halfwords. */
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static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
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{
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tcg_gen_rotri_i32(dest, var, 16);
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}
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#endif
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