b30422231b
Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:
qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
513 lines
20 KiB
C
513 lines
20 KiB
C
/*
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* QEMU RISC-V VirtIO Board
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* RISC-V machine with 16550a UART and VirtIO MMIO
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_test.h"
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#include "hw/riscv/virt.h"
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#include "hw/riscv/boot.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "exec/address-spaces.h"
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#include "hw/pci/pci.h"
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#include "hw/pci-host/gpex.h"
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#include <libfdt.h>
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} virt_memmap[] = {
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[VIRT_DEBUG] = { 0x0, 0x100 },
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[VIRT_MROM] = { 0x1000, 0x11000 },
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[VIRT_TEST] = { 0x100000, 0x1000 },
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[VIRT_CLINT] = { 0x2000000, 0x10000 },
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[VIRT_PLIC] = { 0xc000000, 0x4000000 },
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[VIRT_UART0] = { 0x10000000, 0x100 },
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[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
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[VIRT_DRAM] = { 0x80000000, 0x0 },
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[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
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[VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
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[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
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};
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static void create_pcie_irq_map(void *fdt, char *nodename,
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uint32_t plic_phandle)
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{
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int pin, dev;
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uint32_t
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full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
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uint32_t *irq_map = full_irq_map;
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/* This code creates a standard swizzle of interrupts such that
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* each device's first interrupt is based on it's PCI_SLOT number.
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* (See pci_swizzle_map_irq_fn())
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*
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* We only need one entry per interrupt in the table (not one per
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* possible slot) seeing the interrupt-map-mask will allow the table
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* to wrap to any number of devices.
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*/
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for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
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int devfn = dev * 0x8;
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for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
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int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
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int i = 0;
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irq_map[i] = cpu_to_be32(devfn << 8);
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i += FDT_PCI_ADDR_CELLS;
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irq_map[i] = cpu_to_be32(pin + 1);
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i += FDT_PCI_INT_CELLS;
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irq_map[i++] = cpu_to_be32(plic_phandle);
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i += FDT_PLIC_ADDR_CELLS;
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irq_map[i] = cpu_to_be32(irq_nr);
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irq_map += FDT_INT_MAP_WIDTH;
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}
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}
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qemu_fdt_setprop(fdt, nodename, "interrupt-map",
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full_irq_map, sizeof(full_irq_map));
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
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0x1800, 0, 0, 0x7);
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}
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static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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uint32_t plic_phandle, phandle = 1;
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int i;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[VIRT_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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int cpu_phandle = phandle++;
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int intc_phandle;
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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VIRT_CLOCK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
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intc_phandle = phandle++;
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
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qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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/* Add cpu-topology node */
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
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cpu);
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char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
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qemu_fdt_add_subnode(fdt, core_nodename);
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qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
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g_free(core_nodename);
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g_free(cpu_nodename);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[VIRT_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_CLINT].base,
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0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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plic_phandle = phandle++;
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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(long)memmap[VIRT_PLIC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
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FDT_PLIC_ADDR_CELLS);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
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FDT_PLIC_INT_CELLS);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_PLIC].base,
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0x0, memmap[VIRT_PLIC].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
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qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
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plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
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g_free(cells);
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g_free(nodename);
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for (i = 0; i < VIRTIO_COUNT; i++) {
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nodename = g_strdup_printf("/virtio_mmio@%lx",
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(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
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0x0, memmap[VIRT_VIRTIO].size);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/pci@%lx",
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(long) memmap[VIRT_PCIE_ECAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
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FDT_PCI_ADDR_CELLS);
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qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
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FDT_PCI_INT_CELLS);
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qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"pci-host-ecam-generic");
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
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qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
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qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
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memmap[VIRT_PCIE_ECAM].size /
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PCIE_MMCFG_SIZE_MIN - 1);
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qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
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qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
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0, memmap[VIRT_PCIE_ECAM].size);
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qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
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1, FDT_PCI_RANGE_IOPORT, 2, 0,
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2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
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1, FDT_PCI_RANGE_MMIO,
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2, memmap[VIRT_PCIE_MMIO].base,
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2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
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create_pcie_irq_map(fdt, nodename, plic_phandle);
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g_free(nodename);
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nodename = g_strdup_printf("/test@%lx",
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(long)memmap[VIRT_TEST].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_TEST].base,
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0x0, memmap[VIRT_TEST].size);
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g_free(nodename);
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nodename = g_strdup_printf("/uart@%lx",
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(long)memmap[VIRT_UART0].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_UART0].base,
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0x0, memmap[VIRT_UART0].size);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
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if (cmdline) {
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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}
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g_free(nodename);
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return fdt;
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}
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static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
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hwaddr ecam_base, hwaddr ecam_size,
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hwaddr mmio_base, hwaddr mmio_size,
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hwaddr pio_base,
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DeviceState *plic, bool link_up)
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{
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DeviceState *dev;
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MemoryRegion *ecam_alias, *ecam_reg;
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MemoryRegion *mmio_alias, *mmio_reg;
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qemu_irq irq;
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int i;
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dev = qdev_create(NULL, TYPE_GPEX_HOST);
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qdev_init_nofail(dev);
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ecam_alias = g_new0(MemoryRegion, 1);
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ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
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ecam_reg, 0, ecam_size);
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memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
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mmio_alias = g_new0(MemoryRegion, 1);
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mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
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memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
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mmio_reg, mmio_base, mmio_size);
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memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
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gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
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}
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return dev;
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}
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static void riscv_virt_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = virt_memmap;
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RISCVVirtState *s = g_new0(RISCVVirtState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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char *plic_hart_config;
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size_t plic_hart_config_len;
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int i;
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void *fdt;
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/* Initialize SOC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
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TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
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object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
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main_mem);
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/* create device tree */
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fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
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memmap[VIRT_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
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mask_rom);
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if (machine->firmware) {
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riscv_load_firmware(machine->firmware, memmap[VIRT_DRAM].base);
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}
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if (machine->kernel_filename) {
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uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
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if (machine->initrd_filename) {
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hwaddr start;
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hwaddr end = riscv_load_initrd(machine->initrd_filename,
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machine->ram_size, kernel_entry,
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&start);
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qemu_fdt_setprop_cell(fdt, "/chosen",
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"linux,initrd-start", start);
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qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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end);
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}
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}
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/* reset vector */
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uint32_t reset_vec[8] = {
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0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
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0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
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0xf1402573, /* csrr a0, mhartid */
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#if defined(TARGET_RISCV32)
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0x0182a283, /* lw t0, 24(t0) */
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#elif defined(TARGET_RISCV64)
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0x0182b283, /* ld t0, 24(t0) */
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#endif
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0x00028067, /* jr t0 */
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0x00000000,
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memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */
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0x00000000,
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/* dtb: */
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};
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[VIRT_MROM].base, &address_space_memory);
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/* copy in the device tree */
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if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
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memmap[VIRT_MROM].size - sizeof(reset_vec)) {
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error_report("not enough space to store device-tree");
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exit(1);
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}
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qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
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rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
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memmap[VIRT_MROM].base + sizeof(reset_vec),
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&address_space_memory);
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/* create PLIC hart topology configuration string */
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plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
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plic_hart_config = g_malloc0(plic_hart_config_len);
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for (i = 0; i < smp_cpus; i++) {
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if (i != 0) {
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strncat(plic_hart_config, ",", plic_hart_config_len);
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}
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strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
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plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
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}
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/* MMIO */
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s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
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plic_hart_config,
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VIRT_PLIC_NUM_SOURCES,
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VIRT_PLIC_NUM_PRIORITIES,
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VIRT_PLIC_PRIORITY_BASE,
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VIRT_PLIC_PENDING_BASE,
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VIRT_PLIC_ENABLE_BASE,
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VIRT_PLIC_ENABLE_STRIDE,
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VIRT_PLIC_CONTEXT_BASE,
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VIRT_PLIC_CONTEXT_STRIDE,
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memmap[VIRT_PLIC].size);
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sifive_clint_create(memmap[VIRT_CLINT].base,
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memmap[VIRT_CLINT].size, smp_cpus,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
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sifive_test_create(memmap[VIRT_TEST].base);
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for (i = 0; i < VIRTIO_COUNT; i++) {
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sysbus_create_simple("virtio-mmio",
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memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
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qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
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}
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gpex_pcie_init(system_memory,
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memmap[VIRT_PCIE_ECAM].base,
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memmap[VIRT_PCIE_ECAM].size,
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memmap[VIRT_PCIE_MMIO].base,
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memmap[VIRT_PCIE_MMIO].size,
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memmap[VIRT_PCIE_PIO].base,
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DEVICE(s->plic), true);
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serial_mm_init(system_memory, memmap[VIRT_UART0].base,
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0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
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serial_hd(0), DEVICE_LITTLE_ENDIAN);
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g_free(plic_hart_config);
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}
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static void riscv_virt_board_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
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mc->init = riscv_virt_board_init;
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mc->max_cpus = 8; /* hardcoded limit in BBL */
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mc->default_cpu_type = VIRT_CPU;
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}
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DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
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