Richard Henderson 3ab6e68cd0 accel/tcg: Add tlb_flush_page_bits_by_mmuidx* ... On ARM, the Top Byte Ignore feature means that only 56 bits of the address are significant in the virtual address. We are required to give the entire 64-bit address to FAR_ELx on fault, which means that we do not "clean" the top byte early in TCG. This new interface allows us to flush all 256 possible aliases for a given page, currently missed by tlb_flush_page*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201016210754.818257-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-10-20 16:12:00 +01:00
..
atomic_common.c.inc	meson: rename included C source files to .c.inc	2020-08-21 06:18:30 -04:00
atomic_template.h	qemu/atomic.h: rename atomic_ to qatomic_	2020-09-23 16:07:44 +01:00
cpu-exec-common.c
cpu-exec.c	replay: don't record interrupt poll	2020-10-06 08:34:49 +02:00
cputlb.c	accel/tcg: Add tlb_flush_page_bits_by_mmuidx*	2020-10-20 16:12:00 +01:00
meson.build	cpus: extract out TCG-specific code to accel/tcg	2020-10-05 16:41:22 +02:00
plugin-gen.c
plugin-helpers.h
tcg-all.c	cpus: add handle_interrupt to the CpusAccel interface	2020-10-05 16:41:22 +02:00
tcg-cpus.c	accel/tcg: use current_machine as it is always set for softmmu	2020-10-05 16:41:22 +02:00
tcg-cpus.h	cpus: extract out TCG-specific code to accel/tcg	2020-10-05 16:41:22 +02:00
tcg-runtime-gvec.c
tcg-runtime.c
tcg-runtime.h
trace-events
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate-all.c	cpu-timers, icount: new modules	2020-10-05 16:41:22 +02:00
translate-all.h
translator.c	gdbstub: add reverse step support in replay mode	2020-10-06 08:34:49 +02:00
user-exec-stub.c
user-exec.c	accel/tcg: Fix computing of is_write for MIPS	2020-10-08 05:57:32 -05:00