511 lines
12 KiB
C
511 lines
12 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "vl.h"
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//#define DEBUG
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545
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#define ACPI_DBG_IO_ADDR 0xb044
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typedef struct PIIX4PMState {
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PCIDevice dev;
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uint16_t pmsts;
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uint16_t pmen;
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uint16_t pmcntrl;
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uint8_t apmc;
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uint8_t apms;
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QEMUTimer *tmr_timer;
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int64_t tmr_overflow_time;
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i2c_bus *smbus;
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uint8_t smb_stat;
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uint8_t smb_ctl;
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uint8_t smb_cmd;
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uint8_t smb_addr;
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uint8_t smb_data0;
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uint8_t smb_data1;
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uint8_t smb_data[32];
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uint8_t smb_index;
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} PIIX4PMState;
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define SCI_EN (1 << 0)
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#define SUS_EN (1 << 13)
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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#define SMBHSTSTS 0x00
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#define SMBHSTCNT 0x02
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#define SMBHSTCMD 0x03
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#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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uint32_t d;
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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return d & 0xffffff;
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}
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static int get_pmsts(PIIX4PMState *s)
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{
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int64_t d;
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int pmsts;
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pmsts = s->pmsts;
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN;
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return pmsts;
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}
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static void pm_update_sci(PIIX4PMState *s)
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{
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int sci_level, pmsts;
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int64_t expire_time;
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pmsts = get_pmsts(s);
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sci_level = (((pmsts & s->pmen) &
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->dev.irq[0], sci_level);
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
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qemu_mod_timer(s->tmr_timer, expire_time);
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} else {
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qemu_del_timer(s->tmr_timer);
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}
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}
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static void pm_tmr_timer(void *opaque)
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{
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PIIX4PMState *s = opaque;
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pm_update_sci(s);
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}
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 0x3f;
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switch(addr) {
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case 0x00:
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{
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int64_t d;
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int pmsts;
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pmsts = get_pmsts(s);
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
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}
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s->pmsts &= ~val;
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pm_update_sci(s);
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}
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break;
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case 0x02:
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s->pmen = val;
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pm_update_sci(s);
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break;
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case 0x04:
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{
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN);
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 3;
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switch(sus_typ) {
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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break;
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default:
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break;
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}
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}
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}
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break;
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default:
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break;
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}
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#ifdef DEBUG
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printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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}
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case 0x00:
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val = get_pmsts(s);
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break;
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case 0x02:
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val = s->pmen;
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break;
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case 0x04:
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val = s->pmcntrl;
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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}
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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// PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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}
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case 0x08:
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val = get_pmtmr(s);
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
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return val;
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}
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 1;
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#ifdef DEBUG
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == 0) {
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s->apmc = val;
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= SCI_EN;
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} else if (val == ACPI_DISABLE) {
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s->pmcntrl &= ~SCI_EN;
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}
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if (s->dev.config[0x5b] & (1 << 1)) {
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cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
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}
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} else {
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s->apms = val;
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}
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}
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 1;
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if (addr == 0) {
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val = s->apmc;
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} else {
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val = s->apms;
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}
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#ifdef DEBUG
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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#if defined(DEBUG)
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printf("ACPI: DBG: 0x%08x\n", val);
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#endif
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}
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static void smb_transaction(PIIX4PMState *s)
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{
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uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = s->smb_addr >> 1;
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i2c_bus *bus = s->smbus;
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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switch(prot) {
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case 0x0:
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smbus_quick_command(bus, addr, read);
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break;
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case 0x1:
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if (read) {
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s->smb_data0 = smbus_receive_byte(bus, addr);
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} else {
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smbus_send_byte(bus, addr, cmd);
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}
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break;
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case 0x2:
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if (read) {
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s->smb_data0 = smbus_read_byte(bus, addr, cmd);
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} else {
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smbus_write_byte(bus, addr, cmd, s->smb_data0);
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}
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break;
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case 0x3:
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if (read) {
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uint16_t val;
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val = smbus_read_word(bus, addr, cmd);
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s->smb_data0 = val;
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s->smb_data1 = val >> 8;
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} else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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}
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break;
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case 0x5:
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if (read) {
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
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} else {
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
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}
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break;
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default:
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goto error;
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}
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return;
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error:
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s->smb_stat |= 0x04;
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}
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static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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case SMBHSTSTS:
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s->smb_stat = 0;
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s->smb_index = 0;
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break;
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case SMBHSTCNT:
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s->smb_ctl = val;
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if (val & 0x40)
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smb_transaction(s);
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break;
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case SMBHSTCMD:
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s->smb_cmd = val;
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break;
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case SMBHSTADD:
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s->smb_addr = val;
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break;
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case SMBHSTDAT0:
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s->smb_data0 = val;
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break;
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case SMBHSTDAT1:
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s->smb_data1 = val;
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break;
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case SMBBLKDAT:
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s->smb_data[s->smb_index++] = val;
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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break;
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}
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}
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static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case SMBHSTSTS:
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val = s->smb_stat;
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break;
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case SMBHSTCNT:
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s->smb_index = 0;
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val = s->smb_ctl & 0x1f;
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break;
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case SMBHSTCMD:
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val = s->smb_cmd;
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break;
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case SMBHSTADD:
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val = s->smb_addr;
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break;
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case SMBHSTDAT0:
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val = s->smb_data0;
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break;
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case SMBHSTDAT1:
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val = s->smb_data1;
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break;
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case SMBBLKDAT:
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val = s->smb_data[s->smb_index++];
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void pm_io_space_update(PIIX4PMState *s)
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{
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uint32_t pm_io_base;
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if (s->dev.config[0x80] & 1) {
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xfffe;
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/* XXX: need to improve memory and ioport allocation */
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#if defined(DEBUG)
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printf("PM: mapping to 0x%x\n", pm_io_base);
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#endif
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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}
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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pci_default_write_config(d, address, val, len);
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if (address == 0x80)
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pm_io_space_update((PIIX4PMState *)d);
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}
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static void pm_save(QEMUFile* f,void *opaque)
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{
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PIIX4PMState *s = opaque;
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pci_device_save(&s->dev, f);
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qemu_put_be16s(f, &s->pmsts);
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qemu_put_be16s(f, &s->pmen);
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qemu_put_be16s(f, &s->pmcntrl);
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qemu_put_8s(f, &s->apmc);
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qemu_put_8s(f, &s->apms);
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qemu_put_timer(f, s->tmr_timer);
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qemu_put_be64s(f, &s->tmr_overflow_time);
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}
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static int pm_load(QEMUFile* f,void* opaque,int version_id)
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{
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PIIX4PMState *s = opaque;
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int ret;
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if (version_id > 1)
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return -EINVAL;
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ret = pci_device_load(&s->dev, f);
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if (ret < 0)
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return ret;
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qemu_get_be16s(f, &s->pmsts);
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qemu_get_be16s(f, &s->pmen);
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qemu_get_be16s(f, &s->pmcntrl);
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qemu_get_8s(f, &s->apmc);
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qemu_get_8s(f, &s->apms);
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qemu_get_timer(f, s->tmr_timer);
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qemu_get_be64s(f, &s->tmr_overflow_time);
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pm_io_space_update(s);
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return 0;
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}
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
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{
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PIIX4PMState *s;
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uint8_t *pci_conf;
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s = (PIIX4PMState *)pci_register_device(bus,
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"PM", sizeof(PIIX4PMState),
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devfn, NULL, pm_write_config);
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pci_conf = s->dev.config;
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pci_conf[0x00] = 0x86;
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pci_conf[0x01] = 0x80;
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pci_conf[0x02] = 0x13;
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pci_conf[0x03] = 0x71;
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pci_conf[0x08] = 0x00; // revision number
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pci_conf[0x09] = 0x00;
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pci_conf[0x0a] = 0x80; // other bridge device
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pci_conf[0x0b] = 0x06; // bridge device
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pci_conf[0x0e] = 0x00; // header_type
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pci_conf[0x3d] = 0x01; // interrupt pin 1
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pci_conf[0x40] = 0x01; /* PM io base read only bit */
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register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
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register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
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/* XXX: which specification is used ? The i82731AB has different
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mappings */
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pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
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pci_conf[0x63] = 0x60;
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pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
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(serial_hds[1] != NULL ? 0x90 : 0);
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pci_conf[0x90] = smb_io_base | 1;
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pci_conf[0x91] = smb_io_base >> 8;
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pci_conf[0xd2] = 0x09;
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register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
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register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
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register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
|
|
|
|
s->smbus = i2c_init_bus();
|
|
return s->smbus;
|
|
}
|