369 lines
12 KiB
C
369 lines
12 KiB
C
/*
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* Q35 chipset based pc system emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2009, 2010
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on pc.c, but heavily modified.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/loader.h"
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#include "sysemu/arch_init.h"
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#include "hw/i2c/smbus.h"
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#include "hw/boards.h"
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#include "hw/timer/mc146818rtc.h"
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#include "hw/xen/xen.h"
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#include "sysemu/kvm.h"
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#include "hw/kvm/clock.h"
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#include "hw/pci-host/q35.h"
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#include "exec/address-spaces.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/ich9.h"
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#include "hw/smbios/smbios.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "hw/usb.h"
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#include "qemu/error-report.h"
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#include "migration/migration.h"
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#include "sysemu/numa.h"
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/* ICH9 AHCI has 6 ports */
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#define MAX_SATA_PORTS 6
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/* PC hardware initialisation */
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static void pc_q35_init(MachineState *machine)
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{
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PCMachineState *pcms = PC_MACHINE(machine);
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PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
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Q35PCIHost *q35_host;
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PCIHostState *phb;
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PCIBus *host_bus;
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PCIDevice *lpc;
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DeviceState *lpc_dev;
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BusState *idebus[MAX_SATA_PORTS];
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ISADevice *rtc_state;
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MemoryRegion *system_io = get_system_io();
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MemoryRegion *pci_memory;
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MemoryRegion *rom_memory;
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MemoryRegion *ram_memory;
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GSIState *gsi_state;
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ISABus *isa_bus;
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qemu_irq *i8259;
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int i;
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ICH9LPCState *ich9_lpc;
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PCIDevice *ahci;
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ram_addr_t lowmem;
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DriveInfo *hd[MAX_SATA_PORTS];
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
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* and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
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* also known as MMCFG).
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* If it doesn't, we need to split it in chunks below and above 4G.
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* In any case, try to make sure that guest addresses aligned at
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* 1G boundaries get mapped to host addresses aligned at 1G boundaries.
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*/
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if (machine->ram_size >= 0xb0000000) {
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lowmem = 0x80000000;
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} else {
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lowmem = 0xb0000000;
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}
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/* Handle the machine opt max-ram-below-4g. It is basically doing
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* min(qemu limit, user limit).
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*/
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if (!pcms->max_ram_below_4g) {
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pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */;
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}
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if (lowmem > pcms->max_ram_below_4g) {
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lowmem = pcms->max_ram_below_4g;
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if (machine->ram_size - lowmem > lowmem &&
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lowmem & ((1ULL << 30) - 1)) {
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error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
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") not a multiple of 1G; possible bad performance.",
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pcms->max_ram_below_4g);
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}
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}
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if (machine->ram_size >= lowmem) {
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pcms->above_4g_mem_size = machine->ram_size - lowmem;
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pcms->below_4g_mem_size = lowmem;
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} else {
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pcms->above_4g_mem_size = 0;
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pcms->below_4g_mem_size = machine->ram_size;
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}
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if (xen_enabled()) {
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xen_hvm_init(pcms, &ram_memory);
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}
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pc_cpus_init(pcms);
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kvmclock_create();
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/* pci enabled */
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if (pcmc->pci_enabled) {
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pci_memory = g_new(MemoryRegion, 1);
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memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
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rom_memory = pci_memory;
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} else {
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pci_memory = NULL;
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rom_memory = get_system_memory();
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}
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pc_guest_info_init(pcms);
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if (pcmc->smbios_defaults) {
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/* These values are guest ABI, do not change */
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smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
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mc->name, pcmc->smbios_legacy_mode,
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pcmc->smbios_uuid_encoded,
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SMBIOS_ENTRY_POINT_21);
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}
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/* allocate ram and load rom/bios */
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if (!xen_enabled()) {
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pc_memory_init(pcms, get_system_memory(),
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rom_memory, &ram_memory);
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}
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/* irq lines */
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gsi_state = g_malloc0(sizeof(*gsi_state));
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if (kvm_ioapic_in_kernel()) {
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kvm_pc_setup_irq_routing(pcmc->pci_enabled);
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pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
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GSI_NUM_PINS);
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} else {
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pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
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}
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/* create pci host bus */
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q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
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object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
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object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
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MCH_HOST_PROP_RAM_MEM, NULL);
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object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
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MCH_HOST_PROP_PCI_MEM, NULL);
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object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
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MCH_HOST_PROP_SYSTEM_MEM, NULL);
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object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
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MCH_HOST_PROP_IO_MEM, NULL);
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object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
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PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
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object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
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PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
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/* pci */
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qdev_init_nofail(DEVICE(q35_host));
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phb = PCI_HOST_BRIDGE(q35_host);
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host_bus = phb->bus;
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/* create ISA bus */
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lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
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ICH9_LPC_FUNC), true,
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TYPE_ICH9_LPC_DEVICE);
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object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
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TYPE_HOTPLUG_HANDLER,
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(Object **)&pcms->acpi_dev,
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object_property_allow_set_link,
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OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
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object_property_set_link(OBJECT(machine), OBJECT(lpc),
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PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
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ich9_lpc = ICH9_LPC_DEVICE(lpc);
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lpc_dev = DEVICE(lpc);
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for (i = 0; i < GSI_NUM_PINS; i++) {
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qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]);
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}
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pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
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ICH9_LPC_NB_PIRQS);
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pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
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isa_bus = ich9_lpc->isa_bus;
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if (kvm_pic_in_kernel()) {
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i8259 = kvm_i8259_init(isa_bus);
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} else if (xen_enabled()) {
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i8259 = xen_interrupt_controller_init();
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} else {
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i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
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}
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for (i = 0; i < ISA_NUM_IRQS; i++) {
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gsi_state->i8259_irq[i] = i8259[i];
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}
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g_free(i8259);
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if (pcmc->pci_enabled) {
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ioapic_init_gsi(gsi_state, "q35");
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}
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pc_register_ferr_irq(pcms->gsi[13]);
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assert(pcms->vmport != ON_OFF_AUTO__MAX);
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if (pcms->vmport == ON_OFF_AUTO_AUTO) {
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pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
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}
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/* init basic PC hardware */
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pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy,
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(pcms->vmport != ON_OFF_AUTO_ON), pcms->pit,
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0xff0104);
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/* connect pm stuff to lpc */
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ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
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if (pcms->sata) {
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/* ahci and SATA device, for q35 1 ahci controller is built-in */
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ahci = pci_create_simple_multifunction(host_bus,
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PCI_DEVFN(ICH9_SATA1_DEV,
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ICH9_SATA1_FUNC),
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true, "ich9-ahci");
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idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
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idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
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g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
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ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
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ahci_ide_create_devs(ahci, hd);
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} else {
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idebus[0] = idebus[1] = NULL;
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}
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if (machine_usb(machine)) {
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/* Should we create 6 UHCI according to ich9 spec? */
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ehci_create_ich9_with_companions(host_bus, 0x1d);
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}
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if (pcms->smbus) {
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/* TODO: Populate SPD eeprom data. */
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smbus_eeprom_init(ich9_smb_init(host_bus,
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PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
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0xb100),
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8, NULL, 0);
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}
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pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
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/* the rest devices to which pci devfn is automatically assigned */
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pc_vga_init(isa_bus, host_bus);
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pc_nic_init(isa_bus, host_bus);
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if (pcmc->pci_enabled) {
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pc_pci_device_init(host_bus);
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}
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if (pcms->acpi_nvdimm_state.is_enabled) {
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nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
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pcms->fw_cfg, OBJECT(pcms));
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}
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}
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#define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
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static void pc_init_##suffix(MachineState *machine) \
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{ \
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void (*compat)(MachineState *m) = (compatfn); \
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if (compat) { \
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compat(machine); \
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} \
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pc_q35_init(machine); \
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} \
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DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
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static void pc_q35_machine_options(MachineClass *m)
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{
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m->family = "pc_q35";
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m->desc = "Standard PC (Q35 + ICH9, 2009)";
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m->hot_add_cpu = pc_hot_add_cpu;
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m->units_per_default_bus = 1;
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m->default_machine_opts = "firmware=bios-256k.bin";
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m->default_display = "std";
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m->no_floppy = 1;
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m->has_dynamic_sysbus = true;
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m->max_cpus = 288;
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}
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static void pc_q35_2_9_machine_options(MachineClass *m)
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{
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pc_q35_machine_options(m);
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m->alias = "q35";
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m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
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}
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DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
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pc_q35_2_9_machine_options);
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static void pc_q35_2_8_machine_options(MachineClass *m)
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{
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pc_q35_2_9_machine_options(m);
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m->alias = NULL;
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SET_MACHINE_COMPAT(m, PC_COMPAT_2_8);
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}
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DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
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pc_q35_2_8_machine_options);
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static void pc_q35_2_7_machine_options(MachineClass *m)
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{
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pc_q35_2_8_machine_options(m);
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m->max_cpus = 255;
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SET_MACHINE_COMPAT(m, PC_COMPAT_2_7);
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}
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DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
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pc_q35_2_7_machine_options);
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static void pc_q35_2_6_machine_options(MachineClass *m)
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{
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PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
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pc_q35_2_7_machine_options(m);
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pcmc->legacy_cpu_hotplug = true;
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SET_MACHINE_COMPAT(m, PC_COMPAT_2_6);
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}
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DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
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pc_q35_2_6_machine_options);
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static void pc_q35_2_5_machine_options(MachineClass *m)
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{
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PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
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pc_q35_2_6_machine_options(m);
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pcmc->save_tsc_khz = false;
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m->legacy_fw_cfg_order = 1;
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SET_MACHINE_COMPAT(m, PC_COMPAT_2_5);
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}
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DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
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pc_q35_2_5_machine_options);
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static void pc_q35_2_4_machine_options(MachineClass *m)
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{
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PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
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pc_q35_2_5_machine_options(m);
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m->hw_version = "2.4.0";
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pcmc->broken_reserved_end = true;
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SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
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}
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DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
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pc_q35_2_4_machine_options);
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