3cc1d20823
Port the ARM CPU save/load code to use VMState. Some state is saved in a slightly different order to simplify things -- for example arrays are saved one after the other rather than 'striped', and we always save all 32 VFP registers even if the CPU happens to only have 16. Use one subsection for each feature. This means that we don't need to bump the version field each time that a new feature gets introduced. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed conflicts, updated to use cpu_class_set_vmsd(), updated with new/removed fields since original patch, changed to use custom VMStateInfo for cpsr rather than presave/postload hooks, corrected subsection names so vmload doesn't fail] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
199 lines
6.2 KiB
C
199 lines
6.2 KiB
C
#include "hw/hw.h"
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#include "hw/boards.h"
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static bool vfp_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_VFP);
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}
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static const VMStateDescription vmstate_vfp = {
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.name = "cpu/vfp",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
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VMSTATE_UINT32_ARRAY(env.vfp.xregs, ARMCPU, 16),
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/* TODO: Should use proper FPSCR access functions. */
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VMSTATE_INT32(env.vfp.vec_len, ARMCPU),
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VMSTATE_INT32(env.vfp.vec_stride, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool iwmmxt_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_IWMMXT);
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}
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static const VMStateDescription vmstate_iwmmxt = {
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.name = "cpu/iwmmxt",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
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VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool m_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_M);
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}
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const VMStateDescription vmstate_m = {
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.name = "cpu/m",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
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VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
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VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
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VMSTATE_UINT32(env.v7m.control, ARMCPU),
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VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
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VMSTATE_INT32(env.v7m.exception, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool thumb2ee_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_THUMB2EE);
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}
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static const VMStateDescription vmstate_thumb2ee = {
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.name = "cpu/thumb2ee",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.teecr, ARMCPU),
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VMSTATE_UINT32(env.teehbr, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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uint32_t val = qemu_get_be32(f);
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/* Avoid mode switch when restoring CPSR */
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env->uncached_cpsr = val & CPSR_M;
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cpsr_write(env, val, 0xffffffff);
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return 0;
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}
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static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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qemu_put_be32(f, cpsr_read(env));
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}
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static const VMStateInfo vmstate_cpsr = {
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.name = "cpsr",
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.get = get_cpsr,
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.put = put_cpsr,
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};
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const VMStateDescription vmstate_arm_cpu = {
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.name = "cpu",
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.version_id = 10,
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.minimum_version_id = 10,
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.minimum_version_id_old = 10,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
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{
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.name = "cpsr",
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.version_id = 0,
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.size = sizeof(uint32_t),
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.info = &vmstate_cpsr,
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.flags = VMS_SINGLE,
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.offset = 0,
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},
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VMSTATE_UINT32(env.spsr, ARMCPU),
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VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6),
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VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
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VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
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VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
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VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
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VMSTATE_UINT32(env.cp15.c0_cpuid, ARMCPU),
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VMSTATE_UINT32(env.cp15.c0_cssel, ARMCPU),
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VMSTATE_UINT32(env.cp15.c1_sys, ARMCPU),
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VMSTATE_UINT32(env.cp15.c1_coproc, ARMCPU),
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VMSTATE_UINT32(env.cp15.c1_xscaleauxcr, ARMCPU),
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VMSTATE_UINT32(env.cp15.c1_scr, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_base0, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_base0_hi, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_base1, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_base1_hi, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_control, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_mask, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_base_mask, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_data, ARMCPU),
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VMSTATE_UINT32(env.cp15.c2_insn, ARMCPU),
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VMSTATE_UINT32(env.cp15.c3, ARMCPU),
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VMSTATE_UINT32(env.cp15.c5_insn, ARMCPU),
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VMSTATE_UINT32(env.cp15.c5_data, ARMCPU),
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VMSTATE_UINT32_ARRAY(env.cp15.c6_region, ARMCPU, 8),
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VMSTATE_UINT32(env.cp15.c6_insn, ARMCPU),
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VMSTATE_UINT32(env.cp15.c6_data, ARMCPU),
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VMSTATE_UINT32(env.cp15.c7_par, ARMCPU),
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VMSTATE_UINT32(env.cp15.c7_par_hi, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_insn, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_data, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_pmcr, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_pmcnten, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_pmovsr, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_pmxevtyper, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_pmuserenr, ARMCPU),
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VMSTATE_UINT32(env.cp15.c9_pminten, ARMCPU),
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VMSTATE_UINT32(env.cp15.c13_fcse, ARMCPU),
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VMSTATE_UINT32(env.cp15.c13_context, ARMCPU),
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VMSTATE_UINT32(env.cp15.c13_tls1, ARMCPU),
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VMSTATE_UINT32(env.cp15.c13_tls2, ARMCPU),
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VMSTATE_UINT32(env.cp15.c13_tls3, ARMCPU),
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VMSTATE_UINT32(env.cp15.c15_cpar, ARMCPU),
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VMSTATE_UINT32(env.cp15.c15_power_control, ARMCPU),
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VMSTATE_UINT32(env.cp15.c15_diagnostic, ARMCPU),
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VMSTATE_UINT32(env.cp15.c15_power_diagnostic, ARMCPU),
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VMSTATE_UINT64(env.features, ARMCPU),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (VMStateSubsection[]) {
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{
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.vmsd = &vmstate_vfp,
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.needed = vfp_needed,
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} , {
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.vmsd = &vmstate_iwmmxt,
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.needed = iwmmxt_needed,
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} , {
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.vmsd = &vmstate_m,
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.needed = m_needed,
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} , {
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.vmsd = &vmstate_thumb2ee,
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.needed = thumb2ee_needed,
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} , {
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/* empty */
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}
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}
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};
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