qemu-e2k/target-arm/machine.c
Juan Quintela 3cc1d20823 target-arm: port ARM CPU save/load to use VMState
Port the ARM CPU save/load code to use VMState. Some state is
saved in a slightly different order to simplify things -- for
example arrays are saved one after the other rather than 'striped',
and we always save all 32 VFP registers even if the CPU happens
to only have 16.

Use one subsection for each feature.  This means that we don't need to
bump the version field each time that a new feature gets introduced.

Signed-off-by: Juan Quintela <quintela@redhat.com>
[PMM: fixed conflicts, updated to use cpu_class_set_vmsd(),  updated
 with new/removed fields since original patch, changed to use custom
 VMStateInfo for cpsr rather than presave/postload hooks, corrected
 subsection names so vmload doesn't fail]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19 12:24:19 +01:00

199 lines
6.2 KiB
C

#include "hw/hw.h"
#include "hw/boards.h"
static bool vfp_needed(void *opaque)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
return arm_feature(env, ARM_FEATURE_VFP);
}
static const VMStateDescription vmstate_vfp = {
.name = "cpu/vfp",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
VMSTATE_UINT32_ARRAY(env.vfp.xregs, ARMCPU, 16),
/* TODO: Should use proper FPSCR access functions. */
VMSTATE_INT32(env.vfp.vec_len, ARMCPU),
VMSTATE_INT32(env.vfp.vec_stride, ARMCPU),
VMSTATE_END_OF_LIST()
}
};
static bool iwmmxt_needed(void *opaque)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
return arm_feature(env, ARM_FEATURE_IWMMXT);
}
static const VMStateDescription vmstate_iwmmxt = {
.name = "cpu/iwmmxt",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
VMSTATE_END_OF_LIST()
}
};
static bool m_needed(void *opaque)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
return arm_feature(env, ARM_FEATURE_M);
}
const VMStateDescription vmstate_m = {
.name = "cpu/m",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
VMSTATE_UINT32(env.v7m.control, ARMCPU),
VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
VMSTATE_INT32(env.v7m.exception, ARMCPU),
VMSTATE_END_OF_LIST()
}
};
static bool thumb2ee_needed(void *opaque)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
return arm_feature(env, ARM_FEATURE_THUMB2EE);
}
static const VMStateDescription vmstate_thumb2ee = {
.name = "cpu/thumb2ee",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.teecr, ARMCPU),
VMSTATE_UINT32(env.teehbr, ARMCPU),
VMSTATE_END_OF_LIST()
}
};
static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
/* Avoid mode switch when restoring CPSR */
env->uncached_cpsr = val & CPSR_M;
cpsr_write(env, val, 0xffffffff);
return 0;
}
static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
qemu_put_be32(f, cpsr_read(env));
}
static const VMStateInfo vmstate_cpsr = {
.name = "cpsr",
.get = get_cpsr,
.put = put_cpsr,
};
const VMStateDescription vmstate_arm_cpu = {
.name = "cpu",
.version_id = 10,
.minimum_version_id = 10,
.minimum_version_id_old = 10,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
{
.name = "cpsr",
.version_id = 0,
.size = sizeof(uint32_t),
.info = &vmstate_cpsr,
.flags = VMS_SINGLE,
.offset = 0,
},
VMSTATE_UINT32(env.spsr, ARMCPU),
VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT32(env.cp15.c0_cpuid, ARMCPU),
VMSTATE_UINT32(env.cp15.c0_cssel, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_sys, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_coproc, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_xscaleauxcr, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_scr, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_base0, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_base0_hi, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_base1, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_base1_hi, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_control, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_mask, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_base_mask, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_data, ARMCPU),
VMSTATE_UINT32(env.cp15.c2_insn, ARMCPU),
VMSTATE_UINT32(env.cp15.c3, ARMCPU),
VMSTATE_UINT32(env.cp15.c5_insn, ARMCPU),
VMSTATE_UINT32(env.cp15.c5_data, ARMCPU),
VMSTATE_UINT32_ARRAY(env.cp15.c6_region, ARMCPU, 8),
VMSTATE_UINT32(env.cp15.c6_insn, ARMCPU),
VMSTATE_UINT32(env.cp15.c6_data, ARMCPU),
VMSTATE_UINT32(env.cp15.c7_par, ARMCPU),
VMSTATE_UINT32(env.cp15.c7_par_hi, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_insn, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_data, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_pmcr, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_pmcnten, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_pmovsr, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_pmxevtyper, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_pmuserenr, ARMCPU),
VMSTATE_UINT32(env.cp15.c9_pminten, ARMCPU),
VMSTATE_UINT32(env.cp15.c13_fcse, ARMCPU),
VMSTATE_UINT32(env.cp15.c13_context, ARMCPU),
VMSTATE_UINT32(env.cp15.c13_tls1, ARMCPU),
VMSTATE_UINT32(env.cp15.c13_tls2, ARMCPU),
VMSTATE_UINT32(env.cp15.c13_tls3, ARMCPU),
VMSTATE_UINT32(env.cp15.c15_cpar, ARMCPU),
VMSTATE_UINT32(env.cp15.c15_power_control, ARMCPU),
VMSTATE_UINT32(env.cp15.c15_diagnostic, ARMCPU),
VMSTATE_UINT32(env.cp15.c15_power_diagnostic, ARMCPU),
VMSTATE_UINT64(env.features, ARMCPU),
VMSTATE_END_OF_LIST()
},
.subsections = (VMStateSubsection[]) {
{
.vmsd = &vmstate_vfp,
.needed = vfp_needed,
} , {
.vmsd = &vmstate_iwmmxt,
.needed = iwmmxt_needed,
} , {
.vmsd = &vmstate_m,
.needed = m_needed,
} , {
.vmsd = &vmstate_thumb2ee,
.needed = thumb2ee_needed,
} , {
/* empty */
}
}
};