0a7ac9f9e7
This quirk is a workaround for the following hardware behaviour, on which UEFI (specifically, the bootloader for Windows on Pi2) depends: 1. at boot with an SD card present, the interrupt status/enable registers are initially zero 2. upon enabling it in the interrupt enable register, the card insert bit in the interrupt status register is immediately set 3. after a subsequent controller reset, the card insert interrupt does not fire, even if enabled in the interrupt enable register Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456436130-7048-3-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
96 lines
3.9 KiB
C
96 lines
3.9 KiB
C
/*
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* SD Association Host Standard Specification v2.0 controller emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Mitsyanko Igor <i.mitsyanko@samsung.com>
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* Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
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*
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* Based on MMC controller for Samsung S5PC1xx-based board emulation
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* by Alexey Merkulov and Vladimir Monakhov.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU _General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SDHCI_H
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#define SDHCI_H
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#include "qemu-common.h"
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#include "hw/block/block.h"
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#include "hw/pci/pci.h"
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#include "hw/sysbus.h"
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#include "hw/sd/sd.h"
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/* SD/MMC host controller state */
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typedef struct SDHCIState {
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union {
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PCIDevice pcidev;
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SysBusDevice busdev;
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};
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SDBus sdbus;
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MemoryRegion iomem;
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QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
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QEMUTimer *transfer_timer;
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qemu_irq eject_cb;
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qemu_irq ro_cb;
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qemu_irq irq;
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uint32_t sdmasysad; /* SDMA System Address register */
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uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
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uint16_t blkcnt; /* Blocks count for current transfer */
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uint32_t argument; /* Command Argument Register */
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uint16_t trnmod; /* Transfer Mode Setting Register */
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uint16_t cmdreg; /* Command Register */
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uint32_t rspreg[4]; /* Response Registers 0-3 */
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uint32_t prnsts; /* Present State Register */
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uint8_t hostctl; /* Host Control Register */
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uint8_t pwrcon; /* Power control Register */
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uint8_t blkgap; /* Block Gap Control Register */
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uint8_t wakcon; /* WakeUp Control Register */
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uint16_t clkcon; /* Clock control Register */
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uint8_t timeoutcon; /* Timeout Control Register */
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uint8_t admaerr; /* ADMA Error Status Register */
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uint16_t norintsts; /* Normal Interrupt Status Register */
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uint16_t errintsts; /* Error Interrupt Status Register */
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uint16_t norintstsen; /* Normal Interrupt Status Enable Register */
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uint16_t errintstsen; /* Error Interrupt Status Enable Register */
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uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
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uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
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uint16_t acmd12errsts; /* Auto CMD12 error status register */
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uint64_t admasysaddr; /* ADMA System Address Register */
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uint32_t capareg; /* Capabilities Register */
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uint32_t maxcurr; /* Maximum Current Capabilities Register */
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uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
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uint32_t buf_maxsz;
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uint16_t data_count; /* current element in FIFO buffer */
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uint8_t stopped_state;/* Current SDHC state */
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bool pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */
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bool pending_insert_state;
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/* Buffer Data Port Register - virtual access point to R and W buffers */
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/* Software Reset Register - always reads as 0 */
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/* Force Event Auto CMD12 Error Interrupt Reg - write only */
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/* Force Event Error Interrupt Register- write only */
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/* RO Host Controller Version Register always reads as 0x2401 */
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} SDHCIState;
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#define TYPE_PCI_SDHCI "sdhci-pci"
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#define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI)
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#define TYPE_SYSBUS_SDHCI "generic-sdhci"
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#define SYSBUS_SDHCI(obj) \
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OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI)
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#endif /* SDHCI_H */
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