361 lines
10 KiB
C
361 lines
10 KiB
C
/*
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* ioapic.c IOAPIC emulation logic
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* Split the ioapic logic from apic.c
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* Xiantao Zhang <xiantao.zhang@intel.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "apic.h"
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#include "ioapic.h"
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#include "qemu-timer.h"
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#include "host-utils.h"
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#include "sysbus.h"
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//#define DEBUG_IOAPIC
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#ifdef DEBUG_IOAPIC
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#define DPRINTF(fmt, ...) \
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do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define MAX_IOAPICS 1
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#define IOAPIC_VERSION 0x11
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#define IOAPIC_LVT_DEST_SHIFT 56
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#define IOAPIC_LVT_MASKED_SHIFT 16
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#define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15
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#define IOAPIC_LVT_REMOTE_IRR_SHIFT 14
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#define IOAPIC_LVT_POLARITY_SHIFT 13
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#define IOAPIC_LVT_DELIV_STATUS_SHIFT 12
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#define IOAPIC_LVT_DEST_MODE_SHIFT 11
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#define IOAPIC_LVT_DELIV_MODE_SHIFT 8
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#define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
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#define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
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#define IOAPIC_TRIGGER_EDGE 0
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#define IOAPIC_TRIGGER_LEVEL 1
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/*io{apic,sapic} delivery mode*/
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#define IOAPIC_DM_FIXED 0x0
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#define IOAPIC_DM_LOWEST_PRIORITY 0x1
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#define IOAPIC_DM_PMI 0x2
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#define IOAPIC_DM_NMI 0x4
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#define IOAPIC_DM_INIT 0x5
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#define IOAPIC_DM_SIPI 0x6
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#define IOAPIC_DM_EXTINT 0x7
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#define IOAPIC_DM_MASK 0x7
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#define IOAPIC_VECTOR_MASK 0xff
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#define IOAPIC_IOREGSEL 0x00
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#define IOAPIC_IOWIN 0x10
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#define IOAPIC_REG_ID 0x00
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#define IOAPIC_REG_VER 0x01
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#define IOAPIC_REG_ARB 0x02
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#define IOAPIC_REG_REDTBL_BASE 0x10
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#define IOAPIC_ID 0x00
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#define IOAPIC_ID_SHIFT 24
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#define IOAPIC_ID_MASK 0xf
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#define IOAPIC_VER_ENTRIES_SHIFT 16
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typedef struct IOAPICState IOAPICState;
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struct IOAPICState {
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SysBusDevice busdev;
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MemoryRegion io_memory;
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uint8_t id;
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uint8_t ioregsel;
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uint32_t irr;
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uint64_t ioredtbl[IOAPIC_NUM_PINS];
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};
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static IOAPICState *ioapics[MAX_IOAPICS];
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static void ioapic_service(IOAPICState *s)
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{
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uint8_t i;
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uint8_t trig_mode;
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uint8_t vector;
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uint8_t delivery_mode;
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uint32_t mask;
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uint64_t entry;
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uint8_t dest;
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uint8_t dest_mode;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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mask = 1 << i;
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if (s->irr & mask) {
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entry = s->ioredtbl[i];
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if (!(entry & IOAPIC_LVT_MASKED)) {
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trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
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dest = entry >> IOAPIC_LVT_DEST_SHIFT;
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dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
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delivery_mode =
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(entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
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if (trig_mode == IOAPIC_TRIGGER_EDGE) {
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s->irr &= ~mask;
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} else {
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s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
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}
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if (delivery_mode == IOAPIC_DM_EXTINT) {
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vector = pic_read_irq(isa_pic);
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} else {
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vector = entry & IOAPIC_VECTOR_MASK;
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}
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apic_deliver_irq(dest, dest_mode, delivery_mode,
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vector, trig_mode);
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}
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}
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}
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}
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static void ioapic_set_irq(void *opaque, int vector, int level)
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{
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IOAPICState *s = opaque;
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/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
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* to GSI 2. GSI maps to ioapic 1-1. This is not
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* the cleanest way of doing it but it should work. */
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DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
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if (vector == 0) {
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vector = 2;
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}
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if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
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uint32_t mask = 1 << vector;
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uint64_t entry = s->ioredtbl[vector];
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if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) {
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level = !level;
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}
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if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
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IOAPIC_TRIGGER_LEVEL) {
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/* level triggered */
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if (level) {
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s->irr |= mask;
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ioapic_service(s);
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} else {
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s->irr &= ~mask;
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}
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} else {
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/* According to the 82093AA manual, we must ignore edge requests
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* if the input pin is masked. */
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if (level && !(entry & IOAPIC_LVT_MASKED)) {
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s->irr |= mask;
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ioapic_service(s);
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}
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}
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}
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}
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void ioapic_eoi_broadcast(int vector)
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{
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IOAPICState *s;
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uint64_t entry;
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int i, n;
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for (i = 0; i < MAX_IOAPICS; i++) {
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s = ioapics[i];
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if (!s) {
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continue;
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}
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for (n = 0; n < IOAPIC_NUM_PINS; n++) {
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entry = s->ioredtbl[n];
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if ((entry & IOAPIC_LVT_REMOTE_IRR)
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&& (entry & IOAPIC_VECTOR_MASK) == vector) {
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s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
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if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
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ioapic_service(s);
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}
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}
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}
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}
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}
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static uint64_t
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ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size)
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{
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IOAPICState *s = opaque;
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int index;
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uint32_t val = 0;
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switch (addr & 0xff) {
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case IOAPIC_IOREGSEL:
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val = s->ioregsel;
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break;
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case IOAPIC_IOWIN:
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if (size != 4) {
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break;
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}
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switch (s->ioregsel) {
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case IOAPIC_REG_ID:
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val = s->id << IOAPIC_ID_SHIFT;
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break;
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case IOAPIC_REG_VER:
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val = IOAPIC_VERSION |
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((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
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break;
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case IOAPIC_REG_ARB:
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val = 0;
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break;
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default:
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index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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if (s->ioregsel & 1) {
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val = s->ioredtbl[index] >> 32;
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} else {
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val = s->ioredtbl[index] & 0xffffffff;
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}
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}
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}
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DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
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break;
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}
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return val;
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}
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static void
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ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
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unsigned int size)
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{
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IOAPICState *s = opaque;
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int index;
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switch (addr & 0xff) {
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case IOAPIC_IOREGSEL:
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s->ioregsel = val;
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break;
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case IOAPIC_IOWIN:
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if (size != 4) {
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break;
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}
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DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
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switch (s->ioregsel) {
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case IOAPIC_REG_ID:
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s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
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break;
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case IOAPIC_REG_VER:
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case IOAPIC_REG_ARB:
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break;
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default:
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index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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if (s->ioregsel & 1) {
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s->ioredtbl[index] &= 0xffffffff;
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s->ioredtbl[index] |= (uint64_t)val << 32;
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} else {
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s->ioredtbl[index] &= ~0xffffffffULL;
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s->ioredtbl[index] |= val;
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}
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ioapic_service(s);
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}
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}
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break;
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}
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}
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static int ioapic_post_load(void *opaque, int version_id)
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{
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IOAPICState *s = opaque;
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if (version_id == 1) {
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/* set sane value */
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s->irr = 0;
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}
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return 0;
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}
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static const VMStateDescription vmstate_ioapic = {
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.name = "ioapic",
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.version_id = 3,
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.post_load = ioapic_post_load,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(id, IOAPICState),
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VMSTATE_UINT8(ioregsel, IOAPICState),
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VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */
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VMSTATE_UINT32_V(irr, IOAPICState, 2),
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VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void ioapic_reset(DeviceState *d)
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{
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IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
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int i;
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s->id = 0;
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s->ioregsel = 0;
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s->irr = 0;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
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}
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}
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static const MemoryRegionOps ioapic_io_ops = {
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.read = ioapic_mem_read,
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.write = ioapic_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int ioapic_init1(SysBusDevice *dev)
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{
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IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
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static int ioapic_no;
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if (ioapic_no >= MAX_IOAPICS) {
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return -1;
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}
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memory_region_init_io(&s->io_memory, &ioapic_io_ops, s, "ioapic", 0x1000);
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sysbus_init_mmio(dev, &s->io_memory);
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qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
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ioapics[ioapic_no++] = s;
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return 0;
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}
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static SysBusDeviceInfo ioapic_info = {
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.init = ioapic_init1,
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.qdev.name = "ioapic",
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.qdev.size = sizeof(IOAPICState),
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.qdev.vmsd = &vmstate_ioapic,
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.qdev.reset = ioapic_reset,
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.qdev.no_user = 1,
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};
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static void ioapic_register_devices(void)
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{
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sysbus_register_withprop(&ioapic_info);
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}
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device_init(ioapic_register_devices)
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