Peter Maydell 3d0e3080d8 target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set ... One of the required effects of setting HCR_EL2.TGE is that when SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for all purposes except direct reads. That is, it effectively disables the MMU for the NS EL0/EL1 translation regime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-6-peter.maydell@linaro.org		2018-08-14 17:17:21 +01:00
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alpha
arm	target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set	2018-08-14 17:17:21 +01:00
cris
hppa
i386	i386: implement MSR_SMI_COUNT for TCG	2018-07-30 14:00:11 +02:00
lm32
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-11 12:43:42 +02:00
microblaze	target-microblaze: Rework NOP/zero instruction handling	2018-06-15 09:05:00 +02:00
mips	target/mips: Fix gdbstub to read/write 64 bit FP registers	2018-06-27 20:13:50 +02:00
moxie
nios2
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	target/ppc: fix build on ppc64 host	2018-07-07 12:12:27 +10:00
riscv	RISC-V: Add trailing '\n' to qemu_log() calls	2018-06-08 13:15:33 +01:00
s390x	s390x/cpumodel: fix segmentation fault when baselining models	2018-07-18 14:20:02 +02:00
sh4	target/sh4: Fix translator.c assertion failure for gUSA	2018-07-09 10:34:04 -07:00
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx
tricore
unicore32
xtensa	target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn	2018-08-06 19:07:21 +01:00