3cb1a410ef
These target-specific files use the target-specific CPU state
but lack to include "cpu.h"; i.e.:
../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState'
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
^
../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State'
void mmu_flip_um(CPUNios2State *env, unsigned int um);
^
../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'; did you mean 'CPUState'?
uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
^~~~~~~~~~
CPUState
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220214183144.27402-10-f4bug@amsat.org>
95 lines
3.0 KiB
C
95 lines
3.0 KiB
C
/*
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* Microblaze MMU emulation for qemu.
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*
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* Copyright (c) 2009 Edgar E. Iglesias
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_MICROBLAZE_MMU_H
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#define TARGET_MICROBLAZE_MMU_H
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#include "cpu.h"
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#define MMU_R_PID 0
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#define MMU_R_ZPR 1
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#define MMU_R_TLBX 2
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#define MMU_R_TLBLO 3
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#define MMU_R_TLBHI 4
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#define MMU_R_TLBSX 5
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#define RAM_DATA 1
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#define RAM_TAG 0
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/* Tag portion */
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#define TLB_EPN_MASK MAKE_64BIT_MASK(10, 64 - 10)
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#define TLB_PAGESZ_MASK 0x00000380
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#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
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#define PAGESZ_1K 0
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#define PAGESZ_4K 1
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#define PAGESZ_16K 2
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#define PAGESZ_64K 3
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#define PAGESZ_256K 4
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#define PAGESZ_1M 5
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#define PAGESZ_4M 6
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#define PAGESZ_16M 7
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#define TLB_VALID 0x00000040 /* Entry is valid */
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/* Data portion */
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#define TLB_RPN_MASK MAKE_64BIT_MASK(10, 64 - 10)
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#define TLB_PERM_MASK 0x00000300
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#define TLB_EX 0x00000200 /* Instruction execution allowed */
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#define TLB_WR 0x00000100 /* Writes permitted */
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#define TLB_ZSEL_MASK 0x000000F0
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#define TLB_ZSEL(x) (((x) & 0xF) << 4)
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#define TLB_ATTR_MASK 0x0000000F
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#define TLB_W 0x00000008 /* Caching is write-through */
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#define TLB_I 0x00000004 /* Caching is inhibited */
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#define TLB_M 0x00000002 /* Memory is coherent */
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#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
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/* TLBX */
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#define R_TBLX_MISS_SHIFT 31
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#define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT)
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#define TLB_ENTRIES 64
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typedef struct {
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/* Data and tag brams. */
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uint64_t rams[2][TLB_ENTRIES];
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/* We keep a separate ram for the tids to avoid the 48 bit tag width. */
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uint8_t tids[TLB_ENTRIES];
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/* Control flops. */
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uint32_t regs[3];
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} MicroBlazeMMU;
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typedef struct {
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uint32_t paddr;
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uint32_t vaddr;
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unsigned int size;
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unsigned int idx;
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int prot;
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enum {
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ERR_PROT, ERR_MISS, ERR_HIT
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} err;
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} MicroBlazeMMULookup;
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unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
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target_ulong vaddr, MMUAccessType rw, int mmu_idx);
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uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
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void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
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void mmu_init(MicroBlazeMMU *mmu);
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#endif
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