3d65b958c5
The CTR_EL0 register has some bits which allow the implementation to tell the guest that it does not need to do cache maintenance for data-to-instruction coherence and instruction-to-data coherence. QEMU doesn't emulate caches and so our cache maintenance insns are all NOPs. We already have some models of specific CPUs where we set these bits (e.g. the Neoverse V1), but the 'max' CPU still uses the settings it inherits from Cortex-A57. Set the bits for 'max' as well, so the guest doesn't need to do unnecessary work. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com> |
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| .. | ||
| a32-uncond.decode | ||
| a32.decode | ||
| a64.decode | ||
| arm_ldst.h | ||
| cpu32.c | ||
| cpu64.c | ||
| crypto_helper.c | ||
| helper-a64.c | ||
| helper-a64.h | ||
| helper-mve.h | ||
| helper-sme.h | ||
| helper-sve.h | ||
| hflags.c | ||
| iwmmxt_helper.c | ||
| m_helper.c | ||
| m-nocp.decode | ||
| meson.build | ||
| mte_helper.c | ||
| mve_helper.c | ||
| mve.decode | ||
| neon_helper.c | ||
| neon-dp.decode | ||
| neon-ls.decode | ||
| neon-shared.decode | ||
| op_helper.c | ||
| pauth_helper.c | ||
| psci.c | ||
| sme_helper.c | ||
| sme-fa64.decode | ||
| sme.decode | ||
| sve_helper.c | ||
| sve_ldst_internal.h | ||
| sve.decode | ||
| t16.decode | ||
| t32.decode | ||
| tlb_helper.c | ||
| translate-a32.h | ||
| translate-a64.c | ||
| translate-a64.h | ||
| translate-m-nocp.c | ||
| translate-mve.c | ||
| translate-neon.c | ||
| translate-sme.c | ||
| translate-sve.c | ||
| translate-vfp.c | ||
| translate.c | ||
| translate.h | ||
| vec_helper.c | ||
| vec_internal.h | ||
| vfp-uncond.decode | ||
| vfp.decode | ||