3ddf0b5cde
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3146 c046a42c-6fe2-441c-8c8c-71466251a162
584 lines
18 KiB
C
584 lines
18 KiB
C
/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include "cpu.h"
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#include "exec-all.h"
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enum {
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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};
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/* no MMU emulation */
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int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return TLBRET_MATCH;
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}
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/* fixed mapping MMU emulation */
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int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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if (address <= (int32_t)0x7FFFFFFFUL) {
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if (!(env->CP0_Status & (1 << CP0St_ERL)))
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*physical = address + 0x40000000UL;
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else
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*physical = address;
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} else if (address <= (int32_t)0xBFFFFFFFUL)
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*physical = address & 0x1FFFFFFF;
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else
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return TLBRET_MATCH;
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}
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/* MIPS32/MIPS64 R4000-style MMU emulation */
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int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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uint8_t ASID = env->CP0_EntryHi & 0xFF;
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int i;
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for (i = 0; i < env->tlb_in_use; i++) {
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r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i];
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/* 1k pages are not supported. */
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target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
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target_ulong tag = address & ~mask;
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target_ulong VPN = tlb->VPN & ~mask;
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#ifdef TARGET_MIPS64
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tag &= env->SEGMask;
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#endif
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
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/* TLB match */
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int n = !!(address & mask & ~(mask >> 1));
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/* Check access rights */
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if (!(n ? tlb->V1 : tlb->V0))
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return TLBRET_INVALID;
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if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
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*physical = tlb->PFN[n] | (address & (mask >> 1));
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*prot = PAGE_READ;
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if (n ? tlb->D1 : tlb->D0)
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*prot |= PAGE_WRITE;
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return TLBRET_MATCH;
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}
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return TLBRET_DIRTY;
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}
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}
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return TLBRET_NOMATCH;
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}
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static int get_physical_address (CPUState *env, target_ulong *physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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/* User mode can only access useg/xuseg */
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
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#endif
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int ret = TLBRET_MATCH;
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#if 0
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if (logfile) {
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fprintf(logfile, "user mode %d h %08x\n",
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user_mode, env->hflags);
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}
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#endif
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#ifdef TARGET_MIPS64
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if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
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return TLBRET_BADADDR;
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#else
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if (user_mode && address > 0x7FFFFFFFUL)
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return TLBRET_BADADDR;
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#endif
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if (address <= (int32_t)0x7FFFFFFFUL) {
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/* useg */
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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*physical = address & 0xFFFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = env->map_address(env, physical, prot, address, rw, access_type);
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}
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#ifdef TARGET_MIPS64
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/*
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XXX: Assuming :
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- PABITS = 36 (correct for MIPS64R1)
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*/
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} else if (address < 0x3FFFFFFFFFFFFFFFULL) {
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/* xuseg */
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if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->map_address(env, physical, prot, address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0x7FFFFFFFFFFFFFFFULL) {
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/* xsseg */
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if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->map_address(env, physical, prot, address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0xBFFFFFFFFFFFFFFFULL) {
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/* xkphys */
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/* XXX: check supervisor mode */
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if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
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{
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*physical = address & 0X0000000FFFFFFFFFULL;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0xFFFFFFFF7FFFFFFFULL) {
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/* xkseg */
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/* XXX: check supervisor mode */
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if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
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ret = env->map_address(env, physical, prot, address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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#endif
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} else if (address < (int32_t)0xA0000000UL) {
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/* kseg0 */
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/* XXX: check supervisor mode */
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*physical = address - (int32_t)0x80000000UL;
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*prot = PAGE_READ | PAGE_WRITE;
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} else if (address < (int32_t)0xC0000000UL) {
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/* kseg1 */
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/* XXX: check supervisor mode */
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*physical = address - (int32_t)0xA0000000UL;
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*prot = PAGE_READ | PAGE_WRITE;
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} else if (address < (int32_t)0xE0000000UL) {
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/* kseg2 */
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ret = env->map_address(env, physical, prot, address, rw, access_type);
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} else {
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/* kseg3 */
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/* XXX: check supervisor mode */
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/* XXX: debug segment is not emulated */
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ret = env->map_address(env, physical, prot, address, rw, access_type);
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}
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#if 0
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if (logfile) {
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fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
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address, rw, access_type, *physical, *prot, ret);
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}
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#endif
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return ret;
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}
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#if defined(CONFIG_USER_ONLY)
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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return addr;
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}
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#else
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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target_ulong phys_addr;
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int prot;
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
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return -1;
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return phys_addr;
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}
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void cpu_mips_init_mmu (CPUState *env)
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{
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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target_ulong physical;
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int prot;
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int exception = 0, error_code = 0;
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int access_type;
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int ret = 0;
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if (logfile) {
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#if 0
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cpu_dump_state(env, logfile, fprintf, 0);
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#endif
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fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
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__func__, env->PC, address, rw, is_user, is_softmmu);
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}
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rw &= 1;
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/* data access */
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/* XXX: put correct access by using cpu_restore_state()
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correctly */
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access_type = ACCESS_INT;
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if (env->user_mode_only) {
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/* user mode only emulation */
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ret = TLBRET_NOMATCH;
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goto do_fault;
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}
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ret = get_physical_address(env, &physical, &prot,
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address, rw, access_type);
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if (logfile) {
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fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
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__func__, address, ret, physical, prot);
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}
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if (ret == TLBRET_MATCH) {
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ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot,
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is_user, is_softmmu);
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} else if (ret < 0) {
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do_fault:
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switch (ret) {
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default:
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case TLBRET_BADADDR:
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/* Reference to kernel address from user mode or supervisor mode */
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/* Reference to supervisor address from user mode */
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if (rw)
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exception = EXCP_AdES;
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else
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exception = EXCP_AdEL;
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break;
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */
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if (rw)
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exception = EXCP_TLBS;
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else
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exception = EXCP_TLBL;
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error_code = 1;
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break;
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case TLBRET_INVALID:
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/* TLB match with no valid bit */
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if (rw)
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exception = EXCP_TLBS;
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else
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exception = EXCP_TLBL;
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break;
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case TLBRET_DIRTY:
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/* TLB match but 'D' bit is cleared */
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exception = EXCP_LTLBL;
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break;
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}
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/* Raise exception */
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env->CP0_BadVAddr = address;
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env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
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((address >> 9) & 0x007ffff0);
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env->CP0_EntryHi =
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(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
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#ifdef TARGET_MIPS64
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env->CP0_EntryHi &= env->SEGMask;
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env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
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((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
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((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
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#endif
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env->exception_index = exception;
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env->error_code = error_code;
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ret = 1;
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}
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return ret;
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}
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{
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env->exception_index = EXCP_NONE;
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}
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#else
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void do_interrupt (CPUState *env)
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{
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target_ulong offset;
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int cause = -1;
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if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
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__func__, env->PC, env->CP0_EPC, cause, env->exception_index);
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}
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if (env->exception_index == EXCP_EXT_INTERRUPT &&
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(env->hflags & MIPS_HFLAG_DM))
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env->exception_index = EXCP_DINT;
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offset = 0x180;
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switch (env->exception_index) {
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case EXCP_DSS:
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env->CP0_Debug |= 1 << CP0DB_DSS;
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/* Debug single step cannot be raised inside a delay slot and
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* resume will always occur on the next instruction
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* (but we assume the pc has always been updated during
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* code translation).
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*/
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env->CP0_DEPC = env->PC;
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goto enter_debug_mode;
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case EXCP_DINT:
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env->CP0_Debug |= 1 << CP0DB_DINT;
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goto set_DEPC;
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case EXCP_DIB:
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env->CP0_Debug |= 1 << CP0DB_DIB;
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goto set_DEPC;
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case EXCP_DBp:
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env->CP0_Debug |= 1 << CP0DB_DBp;
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goto set_DEPC;
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case EXCP_DDBS:
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env->CP0_Debug |= 1 << CP0DB_DDBS;
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goto set_DEPC;
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case EXCP_DDBL:
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env->CP0_Debug |= 1 << CP0DB_DDBL;
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set_DEPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_DEPC = env->PC - 4;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_DEPC = env->PC;
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}
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM;
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if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
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env->hflags |= MIPS_HFLAG_64;
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env->hflags &= ~MIPS_HFLAG_UM;
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/* EJTAG probe trap enable is not implemented... */
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->PC = (int32_t)0xBFC00480;
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break;
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case EXCP_RESET:
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cpu_reset(env);
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break;
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case EXCP_SRESET:
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env->CP0_Status |= (1 << CP0St_SR);
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memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
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goto set_error_EPC;
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case EXCP_NMI:
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env->CP0_Status |= (1 << CP0St_NMI);
|
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set_error_EPC:
|
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if (env->hflags & MIPS_HFLAG_BMASK) {
|
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/* If the exception was raised from a delay slot,
|
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come back to the jump. */
|
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env->CP0_ErrorEPC = env->PC - 4;
|
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env->hflags &= ~MIPS_HFLAG_BMASK;
|
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} else {
|
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env->CP0_ErrorEPC = env->PC;
|
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}
|
|
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
|
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if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
|
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env->hflags |= MIPS_HFLAG_64;
|
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env->hflags &= ~MIPS_HFLAG_UM;
|
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
|
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
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env->PC = (int32_t)0xBFC00000;
|
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break;
|
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case EXCP_MCHECK:
|
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cause = 24;
|
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goto set_EPC;
|
|
case EXCP_EXT_INTERRUPT:
|
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cause = 0;
|
|
if (env->CP0_Cause & (1 << CP0Ca_IV))
|
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offset = 0x200;
|
|
goto set_EPC;
|
|
case EXCP_DWATCH:
|
|
cause = 23;
|
|
/* XXX: TODO: manage defered watch exceptions */
|
|
goto set_EPC;
|
|
case EXCP_AdEL:
|
|
cause = 4;
|
|
goto set_EPC;
|
|
case EXCP_AdES:
|
|
cause = 5;
|
|
goto set_EPC;
|
|
case EXCP_TLBL:
|
|
cause = 2;
|
|
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
#ifdef TARGET_MIPS64
|
|
int R = env->CP0_BadVAddr >> 62;
|
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
|
|
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
|
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
|
|
|
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
|
|
offset = 0x080;
|
|
else
|
|
#endif
|
|
offset = 0x000;
|
|
}
|
|
goto set_EPC;
|
|
case EXCP_IBE:
|
|
cause = 6;
|
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goto set_EPC;
|
|
case EXCP_DBE:
|
|
cause = 7;
|
|
goto set_EPC;
|
|
case EXCP_SYSCALL:
|
|
cause = 8;
|
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goto set_EPC;
|
|
case EXCP_BREAK:
|
|
cause = 9;
|
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goto set_EPC;
|
|
case EXCP_RI:
|
|
cause = 10;
|
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goto set_EPC;
|
|
case EXCP_CpU:
|
|
cause = 11;
|
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env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
|
|
(env->error_code << CP0Ca_CE);
|
|
goto set_EPC;
|
|
case EXCP_OVERFLOW:
|
|
cause = 12;
|
|
goto set_EPC;
|
|
case EXCP_TRAP:
|
|
cause = 13;
|
|
goto set_EPC;
|
|
case EXCP_FPE:
|
|
cause = 15;
|
|
goto set_EPC;
|
|
case EXCP_LTLBL:
|
|
cause = 1;
|
|
goto set_EPC;
|
|
case EXCP_TLBS:
|
|
cause = 3;
|
|
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
#ifdef TARGET_MIPS64
|
|
int R = env->CP0_BadVAddr >> 62;
|
|
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
|
|
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
|
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
|
|
|
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
|
|
offset = 0x080;
|
|
else
|
|
#endif
|
|
offset = 0x000;
|
|
}
|
|
set_EPC:
|
|
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
/* If the exception was raised from a delay slot,
|
|
come back to the jump. */
|
|
env->CP0_EPC = env->PC - 4;
|
|
env->CP0_Cause |= (1 << CP0Ca_BD);
|
|
} else {
|
|
env->CP0_EPC = env->PC;
|
|
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
|
}
|
|
env->CP0_Status |= (1 << CP0St_EXL);
|
|
if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
|
|
env->hflags |= MIPS_HFLAG_64;
|
|
env->hflags &= ~MIPS_HFLAG_UM;
|
|
}
|
|
env->hflags &= ~MIPS_HFLAG_BMASK;
|
|
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
|
env->PC = (int32_t)0xBFC00200;
|
|
} else {
|
|
env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
|
}
|
|
env->PC += offset;
|
|
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
|
break;
|
|
default:
|
|
if (logfile) {
|
|
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
|
env->exception_index);
|
|
}
|
|
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
|
exit(1);
|
|
}
|
|
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
|
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
|
|
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
|
|
__func__, env->PC, env->CP0_EPC, cause, env->exception_index,
|
|
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
|
|
env->CP0_DEPC);
|
|
}
|
|
env->exception_index = EXCP_NONE;
|
|
}
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
|
|
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
|
|
{
|
|
r4k_tlb_t *tlb;
|
|
target_ulong addr;
|
|
target_ulong end;
|
|
uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
|
target_ulong mask;
|
|
|
|
tlb = &env->mmu.r4k.tlb[idx];
|
|
/* The qemu TLB is flushed when the ASID changes, so no need to
|
|
flush these entries again. */
|
|
if (tlb->G == 0 && tlb->ASID != ASID) {
|
|
return;
|
|
}
|
|
|
|
if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
|
|
/* For tlbwr, we can shadow the discarded entry into
|
|
a new (fake) TLB entry, as long as the guest can not
|
|
tell that it's there. */
|
|
env->mmu.r4k.tlb[env->tlb_in_use] = *tlb;
|
|
env->tlb_in_use++;
|
|
return;
|
|
}
|
|
|
|
/* 1k pages are not supported. */
|
|
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
|
if (tlb->V0) {
|
|
addr = tlb->VPN & ~mask;
|
|
#ifdef TARGET_MIPS64
|
|
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
|
|
addr |= 0x3FFFFF0000000000ULL;
|
|
}
|
|
#endif
|
|
end = addr | (mask >> 1);
|
|
while (addr < end) {
|
|
tlb_flush_page (env, addr);
|
|
addr += TARGET_PAGE_SIZE;
|
|
}
|
|
}
|
|
if (tlb->V1) {
|
|
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
|
|
#ifdef TARGET_MIPS64
|
|
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
|
|
addr |= 0x3FFFFF0000000000ULL;
|
|
}
|
|
#endif
|
|
end = addr | mask;
|
|
while (addr < end) {
|
|
tlb_flush_page (env, addr);
|
|
addr += TARGET_PAGE_SIZE;
|
|
}
|
|
}
|
|
}
|