qemu-e2k/target-arm
Peter Maydell fa439fc5d7 target-arm: Make *IS TLB maintenance ops affect all CPUs
The ARM architecture defines that the "IS" variants of TLB
maintenance operations must affect all TLBs in the Inner Shareable
domain, which for us means all CPUs. We were incorrectly implementing
these to only affect the current CPU, which meant that SMP TCG
operation was unstable.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1410274883-9578-3-git-send-email-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
2014-09-12 14:06:50 +01:00
..
arm_ldst.h
arm-semi.c
cpu64.c target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values 2014-08-29 15:00:28 +01:00
cpu-qom.h target-arm: Adjust debug ID registers per-CPU 2014-08-19 19:02:03 +01:00
cpu.c target-arm: Implement handling of fired watchpoints 2014-09-12 14:06:49 +01:00
cpu.h target-arm: Implement setting of watchpoints 2014-09-12 14:06:49 +01:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target-arm: Make far_el1 an array 2014-08-04 14:41:54 +01:00
helper-a64.h
helper.c target-arm: Make *IS TLB maintenance ops affect all CPUs 2014-09-12 14:06:50 +01:00
helper.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
internals.h target-arm: Implement handling of fired watchpoints 2014-09-12 14:06:49 +01:00
iwmmxt_helper.c
kvm32.c target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs 2014-07-08 13:05:11 +01:00
kvm64.c target-arm: A64: Break out aarch64_save/restore_sp 2014-08-04 14:41:54 +01:00
kvm_arm.h target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
kvm-consts.h arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 2014-08-19 19:02:25 +01:00
kvm-stub.c
kvm.c target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
machine.c target-arm: Implement setting of watchpoints 2014-09-12 14:06:49 +01:00
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c target-arm: Implement handling of fired watchpoints 2014-09-12 14:06:49 +01:00
translate-a64.c target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
translate.c target-arm: Implement ARMv8 single-stepping for AArch32 code 2014-08-19 19:02:03 +01:00
translate.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00