LIU Zhiwei 3e09396e36 target/riscv: fix vector index load/store constraints ... Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-22 09:39:46 -07:00
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alpha
arm	hw/arm/virt: Enable MTE via a machine property	2020-07-20 11:35:15 +01:00
avr	target/avr/disas: Fix store instructions display order	2020-07-11 11:02:05 +02:00
cris
hppa
i386	i386: hvf: Explicitly set CR4 guest/host mask	2020-07-16 14:15:13 -04:00
lm32
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2020-07-06 21:39:57 +02:00
microblaze
mips	target/mips: Fix ADD.S FPU instruction	2020-07-14 21:49:33 +02:00
moxie
nios2	target/nios2: Use gen_io_start around wrctl instruction	2020-07-13 14:36:11 +01:00
openrisc
ppc	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
riscv	target/riscv: fix vector index load/store constraints	2020-07-22 09:39:46 -07:00
rx
s390x	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
sh4
sparc	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
tilegx
tricore
unicore32
xtensa	target/xtensa fixes for 5.1:	2020-06-25 21:20:45 +01:00