352 lines
12 KiB
C
352 lines
12 KiB
C
/*
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* ARM GICv3 support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2012 Linaro Limited
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Peter Maydell
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* Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qom/cpu.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "gicv3_internal.h"
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#include "hw/arm/linux-boot-if.h"
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static void gicv3_pre_save(void *opaque)
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{
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GICv3State *s = (GICv3State *)opaque;
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ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
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if (c->pre_save) {
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c->pre_save(s);
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}
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}
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static int gicv3_post_load(void *opaque, int version_id)
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{
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GICv3State *s = (GICv3State *)opaque;
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ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
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if (c->post_load) {
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c->post_load(s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_gicv3_cpu = {
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.name = "arm_gicv3_cpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(level, GICv3CPUState),
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VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
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VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
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VMSTATE_UINT32(gicr_waker, GICv3CPUState),
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VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
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VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
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VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
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VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
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VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
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VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
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VMSTATE_UINT32(edge_trigger, GICv3CPUState),
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VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
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VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
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VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
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VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
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VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
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VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
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VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
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VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
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VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_gicv3 = {
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.name = "arm_gicv3",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = gicv3_pre_save,
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.post_load = gicv3_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(gicd_ctlr, GICv3State),
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VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
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VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
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VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
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VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
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DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
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VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
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vmstate_gicv3_cpu, GICv3CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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const MemoryRegionOps *ops)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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int i;
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/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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* GPIO array layout is thus:
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* [0..N-1] spi
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* [N..N+31] PPIs for CPU 0
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* [N+32..N+63] PPIs for CPU 1
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* ...
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*/
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i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
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qdev_init_gpio_in(DEVICE(s), handler, i);
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
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}
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memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
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"gicv3_dist", 0x10000);
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memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
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"gicv3_redist", 0x20000 * s->num_cpu);
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sysbus_init_mmio(sbd, &s->iomem_dist);
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sysbus_init_mmio(sbd, &s->iomem_redist);
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}
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static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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{
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GICv3State *s = ARM_GICV3_COMMON(dev);
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int i;
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/* revision property is actually reserved and currently used only in order
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* to keep the interface compatible with GICv2 code, avoiding extra
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* conditions. However, in future it could be used, for example, if we
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* implement GICv4.
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*/
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if (s->revision != 3) {
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error_setg(errp, "unsupported GIC revision %d", s->revision);
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return;
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}
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if (s->num_irq > GICV3_MAXIRQ) {
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error_setg(errp,
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"requested %u interrupt lines exceeds GIC maximum %d",
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s->num_irq, GICV3_MAXIRQ);
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return;
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}
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if (s->num_irq < GIC_INTERNAL) {
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error_setg(errp,
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"requested %u interrupt lines is below GIC minimum %d",
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s->num_irq, GIC_INTERNAL);
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return;
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}
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/* ITLinesNumber is represented as (N / 32) - 1, so this is an
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* implementation imposed restriction, not an architectural one,
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* so we don't have to deal with bitfields where only some of the
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* bits in a 32-bit word should be valid.
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*/
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if (s->num_irq % 32) {
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error_setg(errp,
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"%d interrupt lines unsupported: not divisible by 32",
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s->num_irq);
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return;
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}
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s->cpu = g_new0(GICv3CPUState, s->num_cpu);
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for (i = 0; i < s->num_cpu; i++) {
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CPUState *cpu = qemu_get_cpu(i);
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uint64_t cpu_affid;
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int last;
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s->cpu[i].cpu = cpu;
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s->cpu[i].gic = s;
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/* Pre-construct the GICR_TYPER:
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* For our implementation:
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* Top 32 bits are the affinity value of the associated CPU
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* CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
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* Processor_Number == CPU index starting from 0
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* DPGS == 0 (GICR_CTLR.DPG* not supported)
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* Last == 1 if this is the last redistributor in a series of
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* contiguous redistributor pages
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* DirectLPI == 0 (direct injection of LPIs not supported)
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* VLPIS == 0 (virtual LPIs not supported)
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* PLPIS == 0 (physical LPIs not supported)
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*/
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cpu_affid = object_property_get_int(OBJECT(cpu), "mp-affinity", NULL);
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last = (i == s->num_cpu - 1);
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/* The CPU mp-affinity property is in MPIDR register format; squash
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* the affinity bytes into 32 bits as the GICR_TYPER has them.
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*/
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cpu_affid = (cpu_affid & 0xFF00000000ULL >> 8) | (cpu_affid & 0xFFFFFF);
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s->cpu[i].gicr_typer = (cpu_affid << 32) |
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(1 << 24) |
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(i << 8) |
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(last << 4);
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}
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}
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static void arm_gicv3_common_reset(DeviceState *dev)
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{
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GICv3State *s = ARM_GICV3_COMMON(dev);
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int i;
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for (i = 0; i < s->num_cpu; i++) {
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GICv3CPUState *cs = &s->cpu[i];
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cs->level = 0;
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cs->gicr_ctlr = 0;
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cs->gicr_statusr[GICV3_S] = 0;
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cs->gicr_statusr[GICV3_NS] = 0;
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cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
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cs->gicr_propbaser = 0;
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cs->gicr_pendbaser = 0;
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/* If we're resetting a TZ-aware GIC as if secure firmware
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* had set it up ready to start a kernel in non-secure, we
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* need to set interrupts to group 1 so the kernel can use them.
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* Otherwise they reset to group 0 like the hardware.
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*/
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if (s->irq_reset_nonsecure) {
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cs->gicr_igroupr0 = 0xffffffff;
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} else {
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cs->gicr_igroupr0 = 0;
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}
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cs->gicr_ienabler0 = 0;
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cs->gicr_ipendr0 = 0;
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cs->gicr_iactiver0 = 0;
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cs->edge_trigger = 0xffff;
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cs->gicr_igrpmodr0 = 0;
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cs->gicr_nsacr = 0;
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memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
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cs->hppi.prio = 0xff;
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/* State in the CPU interface must *not* be reset here, because it
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* is part of the CPU's reset domain, not the GIC device's.
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*/
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}
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/* For our implementation affinity routing is always enabled */
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if (s->security_extn) {
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s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
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} else {
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s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
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}
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s->gicd_statusr[GICV3_S] = 0;
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s->gicd_statusr[GICV3_NS] = 0;
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memset(s->group, 0, sizeof(s->group));
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memset(s->grpmod, 0, sizeof(s->grpmod));
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memset(s->enabled, 0, sizeof(s->enabled));
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memset(s->pending, 0, sizeof(s->pending));
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memset(s->active, 0, sizeof(s->active));
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memset(s->level, 0, sizeof(s->level));
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memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
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memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
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memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
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memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
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/* GICD_IROUTER are UNKNOWN at reset so in theory the guest must
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* write these to get sane behaviour and we need not populate the
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* pointer cache here; however having the cache be different for
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* "happened to be 0 from reset" and "guest wrote 0" would be
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* too confusing.
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*/
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gicv3_cache_all_target_cpustates(s);
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if (s->irq_reset_nonsecure) {
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/* If we're resetting a TZ-aware GIC as if secure firmware
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* had set it up ready to start a kernel in non-secure, we
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* need to set interrupts to group 1 so the kernel can use them.
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* Otherwise they reset to group 0 like the hardware.
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*/
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for (i = GIC_INTERNAL; i < s->num_irq; i++) {
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gicv3_gicd_group_set(s, i);
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}
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}
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}
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static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
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bool secure_boot)
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{
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GICv3State *s = ARM_GICV3_COMMON(obj);
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if (s->security_extn && !secure_boot) {
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/* We're directly booting a kernel into NonSecure. If this GIC
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* implements the security extensions then we must configure it
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* to have all the interrupts be NonSecure (this is a job that
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* is done by the Secure boot firmware in real hardware, and in
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* this mode QEMU is acting as a minimalist firmware-and-bootloader
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* equivalent).
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*/
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s->irq_reset_nonsecure = true;
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}
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}
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static Property arm_gicv3_common_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
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DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
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DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
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dc->reset = arm_gicv3_common_reset;
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dc->realize = arm_gicv3_common_realize;
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dc->props = arm_gicv3_common_properties;
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dc->vmsd = &vmstate_gicv3;
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albifc->arm_linux_init = arm_gic_common_linux_init;
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}
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static const TypeInfo arm_gicv3_common_type = {
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.name = TYPE_ARM_GICV3_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GICv3State),
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.class_size = sizeof(ARMGICv3CommonClass),
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.class_init = arm_gicv3_common_class_init,
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.abstract = true,
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.interfaces = (InterfaceInfo []) {
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{ TYPE_ARM_LINUX_BOOT_IF },
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{ },
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},
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};
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static void register_types(void)
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{
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type_register_static(&arm_gicv3_common_type);
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}
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type_init(register_types)
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