qemu-e2k/include/hw/riscv
Alistair Francis 3ed2b8ac2d hw/riscv: Use the CPU to determine if 32-bit
Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.

This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
2020-12-17 21:56:44 -08:00
..
boot_opensbi.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
boot.h hw/riscv: Use the CPU to determine if 32-bit 2020-12-17 21:56:44 -08:00
microchip_pfsoc.h hw/riscv: microchip_pfsoc: add QSPI NOR flash 2020-12-17 21:56:43 -08:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
riscv_hart.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
sifive_cpu.h
sifive_e.h sifive_e: Rename memmap enum constants 2020-09-18 13:49:48 -04:00
sifive_u.h hw/riscv: sifive_u: Allow specifying the CPU 2020-10-22 12:00:22 -07:00
spike.h riscv: spike: Remove target macro conditionals 2020-12-17 21:56:44 -08:00
virt.h riscv: virt: Remove target macro conditionals 2020-12-17 21:56:44 -08:00