274 lines
7.1 KiB
C
274 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch ipi interrupt support
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/intc/loongarch_ipi.h"
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#include "hw/irq.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "exec/address-spaces.h"
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#include "hw/loongarch/virt.h"
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#include "migration/vmstate.h"
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#include "target/loongarch/internals.h"
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#include "trace.h"
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static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size)
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{
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IPICore *s = opaque;
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uint64_t ret = 0;
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int index = 0;
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addr &= 0xff;
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switch (addr) {
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case CORE_STATUS_OFF:
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ret = s->status;
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break;
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case CORE_EN_OFF:
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ret = s->en;
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break;
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case CORE_SET_OFF:
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ret = 0;
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break;
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case CORE_CLEAR_OFF:
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ret = 0;
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break;
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case CORE_BUF_20 ... CORE_BUF_38 + 4:
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index = (addr - CORE_BUF_20) >> 2;
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ret = s->buf[index];
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
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break;
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}
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trace_loongarch_ipi_read(size, (uint64_t)addr, ret);
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return ret;
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}
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static void send_ipi_data(CPULoongArchState *env, target_ulong val, target_ulong addr)
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{
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int i, mask = 0, data = 0;
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/*
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* bit 27-30 is mask for byte writing,
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* if the mask is 0, we need not to do anything.
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*/
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if ((val >> 27) & 0xf) {
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data = address_space_ldl(&env->address_space_iocsr, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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for (i = 0; i < 4; i++) {
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/* get mask for byte writing */
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if (val & (0x1 << (27 + i))) {
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mask |= 0xff << (i * 8);
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}
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}
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}
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data &= mask;
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data |= (val >> 32) & ~mask;
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address_space_stl(&env->address_space_iocsr, addr,
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data, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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static void ipi_send(uint64_t val)
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{
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int cpuid, data;
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CPULoongArchState *env;
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CPUState *cs;
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LoongArchCPU *cpu;
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cpuid = (val >> 16) & 0x3ff;
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/* IPI status vector */
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data = 1 << (val & 0x1f);
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cs = qemu_get_cpu(cpuid);
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cpu = LOONGARCH_CPU(cs);
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env = &cpu->env;
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address_space_stl(&env->address_space_iocsr, 0x1008,
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data, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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static void mail_send(uint64_t val)
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{
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int cpuid;
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hwaddr addr;
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CPULoongArchState *env;
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CPUState *cs;
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LoongArchCPU *cpu;
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cpuid = (val >> 16) & 0x3ff;
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addr = 0x1020 + (val & 0x1c);
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cs = qemu_get_cpu(cpuid);
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cpu = LOONGARCH_CPU(cs);
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env = &cpu->env;
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send_ipi_data(env, val, addr);
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}
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static void any_send(uint64_t val)
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{
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int cpuid;
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hwaddr addr;
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CPULoongArchState *env;
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cpuid = (val >> 16) & 0x3ff;
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addr = val & 0xffff;
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CPUState *cs = qemu_get_cpu(cpuid);
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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env = &cpu->env;
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send_ipi_data(env, val, addr);
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}
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static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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IPICore *s = opaque;
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int index = 0;
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addr &= 0xff;
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trace_loongarch_ipi_write(size, (uint64_t)addr, val);
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switch (addr) {
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case CORE_STATUS_OFF:
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qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
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break;
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case CORE_EN_OFF:
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s->en = val;
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break;
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case CORE_SET_OFF:
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s->status |= val;
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if (s->status != 0 && (s->status & s->en) != 0) {
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qemu_irq_raise(s->irq);
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}
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break;
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case CORE_CLEAR_OFF:
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s->status &= ~val;
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if (s->status == 0 && s->en != 0) {
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qemu_irq_lower(s->irq);
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}
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break;
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case CORE_BUF_20 ... CORE_BUF_38 + 4:
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index = (addr - CORE_BUF_20) >> 2;
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s->buf[index] = val;
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break;
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case IOCSR_IPI_SEND:
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ipi_send(val);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
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break;
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}
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}
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static const MemoryRegionOps loongarch_ipi_ops = {
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.read = loongarch_ipi_readl,
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.write = loongarch_ipi_writel,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 4,
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.valid.max_access_size = 8,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* mail send and any send only support writeq */
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static void loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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addr &= 0xfff;
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switch (addr) {
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case MAIL_SEND_OFFSET:
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mail_send(val);
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break;
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case ANY_SEND_OFFSET:
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any_send(val);
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break;
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default:
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break;
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}
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}
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static const MemoryRegionOps loongarch_ipi64_ops = {
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.write = loongarch_ipi_writeq,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void loongarch_ipi_init(Object *obj)
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{
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int cpu;
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LoongArchMachineState *lams;
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LoongArchIPI *s = LOONGARCH_IPI(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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Object *machine = qdev_get_machine();
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ObjectClass *mc = object_get_class(machine);
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/* 'lams' should be initialized */
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if (!strcmp(MACHINE_CLASS(mc)->name, "none")) {
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return;
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}
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lams = LOONGARCH_MACHINE(machine);
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for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
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memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_ops,
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&lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
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sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]);
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memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ipi64_ops,
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&lams->ipi_core[cpu], "loongarch_ipi64_iocsr", 0x118);
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sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem[cpu]);
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qdev_init_gpio_out(DEVICE(obj), &lams->ipi_core[cpu].irq, 1);
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}
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}
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static const VMStateDescription vmstate_ipi_core = {
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.name = "ipi-single",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(status, IPICore),
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VMSTATE_UINT32(en, IPICore),
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VMSTATE_UINT32(set, IPICore),
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VMSTATE_UINT32(clear, IPICore),
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VMSTATE_UINT32_ARRAY(buf, IPICore, MAX_IPI_MBX_NUM * 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_loongarch_ipi = {
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.name = TYPE_LOONGARCH_IPI,
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(ipi_core, LoongArchMachineState,
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MAX_IPI_CORE_NUM, 0,
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vmstate_ipi_core, IPICore),
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VMSTATE_END_OF_LIST()
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}
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};
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static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_loongarch_ipi;
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}
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static const TypeInfo loongarch_ipi_info = {
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.name = TYPE_LOONGARCH_IPI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LoongArchIPI),
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.instance_init = loongarch_ipi_init,
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.class_init = loongarch_ipi_class_init,
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};
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static void loongarch_ipi_register_types(void)
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{
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type_register_static(&loongarch_ipi_info);
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}
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type_init(loongarch_ipi_register_types)
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