666 lines
19 KiB
C
666 lines
19 KiB
C
#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/error-report.h"
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#include "hw/mem/memory-device.h"
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#include "hw/mem/pc-dimm.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/pmem.h"
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#include "qemu/range.h"
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#include "qemu/rcu.h"
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#include "sysemu/hostmem.h"
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#include "sysemu/numa.h"
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#include "hw/cxl/cxl.h"
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#include "hw/pci/msix.h"
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#define DWORD_BYTE 4
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/* Default CDAT entries for a memory region */
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enum {
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CT3_CDAT_DSMAS,
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CT3_CDAT_DSLBIS0,
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CT3_CDAT_DSLBIS1,
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CT3_CDAT_DSLBIS2,
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CT3_CDAT_DSLBIS3,
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CT3_CDAT_DSEMTS,
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CT3_CDAT_NUM_ENTRIES
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};
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static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
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int dsmad_handle, MemoryRegion *mr)
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{
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g_autofree CDATDsmas *dsmas = NULL;
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g_autofree CDATDslbis *dslbis0 = NULL;
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g_autofree CDATDslbis *dslbis1 = NULL;
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g_autofree CDATDslbis *dslbis2 = NULL;
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g_autofree CDATDslbis *dslbis3 = NULL;
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g_autofree CDATDsemts *dsemts = NULL;
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dsmas = g_malloc(sizeof(*dsmas));
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if (!dsmas) {
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return -ENOMEM;
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}
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*dsmas = (CDATDsmas) {
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.header = {
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.type = CDAT_TYPE_DSMAS,
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.length = sizeof(*dsmas),
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},
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.DSMADhandle = dsmad_handle,
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.flags = CDAT_DSMAS_FLAG_NV,
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.DPA_base = 0,
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.DPA_length = int128_get64(mr->size),
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};
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/* For now, no memory side cache, plausiblish numbers */
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dslbis0 = g_malloc(sizeof(*dslbis0));
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if (!dslbis0) {
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return -ENOMEM;
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}
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*dslbis0 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis0),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_READ_LATENCY,
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.entry_base_unit = 10000, /* 10ns base */
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.entry[0] = 15, /* 150ns */
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};
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dslbis1 = g_malloc(sizeof(*dslbis1));
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if (!dslbis1) {
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return -ENOMEM;
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}
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*dslbis1 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis1),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_WRITE_LATENCY,
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.entry_base_unit = 10000,
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.entry[0] = 25, /* 250ns */
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};
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dslbis2 = g_malloc(sizeof(*dslbis2));
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if (!dslbis2) {
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return -ENOMEM;
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}
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*dslbis2 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis2),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_READ_BANDWIDTH,
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.entry_base_unit = 1000, /* GB/s */
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.entry[0] = 16,
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};
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dslbis3 = g_malloc(sizeof(*dslbis3));
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if (!dslbis3) {
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return -ENOMEM;
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}
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*dslbis3 = (CDATDslbis) {
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.header = {
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.type = CDAT_TYPE_DSLBIS,
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.length = sizeof(*dslbis3),
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},
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.handle = dsmad_handle,
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.flags = HMAT_LB_MEM_MEMORY,
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.data_type = HMAT_LB_DATA_WRITE_BANDWIDTH,
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.entry_base_unit = 1000, /* GB/s */
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.entry[0] = 16,
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};
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dsemts = g_malloc(sizeof(*dsemts));
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if (!dsemts) {
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return -ENOMEM;
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}
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*dsemts = (CDATDsemts) {
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.header = {
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.type = CDAT_TYPE_DSEMTS,
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.length = sizeof(*dsemts),
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},
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.DSMAS_handle = dsmad_handle,
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/* Reserved - the non volatile from DSMAS matters */
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.EFI_memory_type_attr = 2,
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.DPA_offset = 0,
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.DPA_length = int128_get64(mr->size),
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};
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/* Header always at start of structure */
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cdat_table[CT3_CDAT_DSMAS] = g_steal_pointer(&dsmas);
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cdat_table[CT3_CDAT_DSLBIS0] = g_steal_pointer(&dslbis0);
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cdat_table[CT3_CDAT_DSLBIS1] = g_steal_pointer(&dslbis1);
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cdat_table[CT3_CDAT_DSLBIS2] = g_steal_pointer(&dslbis2);
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cdat_table[CT3_CDAT_DSLBIS3] = g_steal_pointer(&dslbis3);
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cdat_table[CT3_CDAT_DSEMTS] = g_steal_pointer(&dsemts);
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return 0;
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}
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static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
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{
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g_autofree CDATSubHeader **table = NULL;
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MemoryRegion *nonvolatile_mr;
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CXLType3Dev *ct3d = priv;
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int dsmad_handle = 0;
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int rc;
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if (!ct3d->hostmem) {
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return 0;
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}
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nonvolatile_mr = host_memory_backend_get_memory(ct3d->hostmem);
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if (!nonvolatile_mr) {
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return -EINVAL;
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}
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table = g_malloc0(CT3_CDAT_NUM_ENTRIES * sizeof(*table));
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if (!table) {
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return -ENOMEM;
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}
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rc = ct3_build_cdat_entries_for_mr(table, dsmad_handle++, nonvolatile_mr);
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if (rc < 0) {
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return rc;
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}
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*cdat_table = g_steal_pointer(&table);
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return CT3_CDAT_NUM_ENTRIES;
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}
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static void ct3_free_cdat_table(CDATSubHeader **cdat_table, int num, void *priv)
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{
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int i;
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for (i = 0; i < num; i++) {
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g_free(cdat_table[i]);
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}
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g_free(cdat_table);
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}
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static bool cxl_doe_cdat_rsp(DOECap *doe_cap)
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{
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CDATObject *cdat = &CXL_TYPE3(doe_cap->pdev)->cxl_cstate.cdat;
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uint16_t ent;
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void *base;
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uint32_t len;
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CDATReq *req = pcie_doe_get_write_mbox_ptr(doe_cap);
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CDATRsp rsp;
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assert(cdat->entry_len);
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/* Discard if request length mismatched */
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if (pcie_doe_get_obj_len(req) <
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DIV_ROUND_UP(sizeof(CDATReq), DWORD_BYTE)) {
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return false;
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}
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ent = req->entry_handle;
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base = cdat->entry[ent].base;
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len = cdat->entry[ent].length;
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rsp = (CDATRsp) {
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.header = {
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.vendor_id = CXL_VENDOR_ID,
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.data_obj_type = CXL_DOE_TABLE_ACCESS,
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.reserved = 0x0,
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.length = DIV_ROUND_UP((sizeof(rsp) + len), DWORD_BYTE),
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},
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.rsp_code = CXL_DOE_TAB_RSP,
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.table_type = CXL_DOE_TAB_TYPE_CDAT,
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.entry_handle = (ent < cdat->entry_len - 1) ?
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ent + 1 : CXL_DOE_TAB_ENT_MAX,
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};
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memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp));
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memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), DWORD_BYTE),
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base, len);
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doe_cap->read_mbox_len += rsp.header.length;
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return true;
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}
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static uint32_t ct3d_config_read(PCIDevice *pci_dev, uint32_t addr, int size)
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{
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CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
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uint32_t val;
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if (pcie_doe_read_config(&ct3d->doe_cdat, addr, size, &val)) {
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return val;
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}
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return pci_default_read_config(pci_dev, addr, size);
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}
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static void ct3d_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t val,
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int size)
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{
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CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
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pcie_doe_write_config(&ct3d->doe_cdat, addr, val, size);
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pci_default_write_config(pci_dev, addr, val, size);
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}
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/*
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* Null value of all Fs suggested by IEEE RA guidelines for use of
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* EU, OUI and CID
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*/
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#define UI64_NULL ~(0ULL)
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static void build_dvsecs(CXLType3Dev *ct3d)
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{
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CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
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uint8_t *dvsec;
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dvsec = (uint8_t *)&(CXLDVSECDevice){
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.cap = 0x1e,
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.ctrl = 0x2,
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.status2 = 0x2,
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.range1_size_hi = ct3d->hostmem->size >> 32,
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.range1_size_lo = (2 << 5) | (2 << 2) | 0x3 |
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(ct3d->hostmem->size & 0xF0000000),
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.range1_base_hi = 0,
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.range1_base_lo = 0,
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};
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cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
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PCIE_CXL_DEVICE_DVSEC_LENGTH,
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PCIE_CXL_DEVICE_DVSEC,
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PCIE_CXL2_DEVICE_DVSEC_REVID, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
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.rsvd = 0,
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.reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
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.reg0_base_hi = 0,
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.reg1_base_lo = RBI_CXL_DEVICE_REG | CXL_DEVICE_REG_BAR_IDX,
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.reg1_base_hi = 0,
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};
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cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
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REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
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REG_LOC_DVSEC_REVID, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECDeviceGPF){
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.phase2_duration = 0x603, /* 3 seconds */
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.phase2_power = 0x33, /* 0x33 miliwatts */
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};
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cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
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GPF_DEVICE_DVSEC_LENGTH, GPF_DEVICE_DVSEC,
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GPF_DEVICE_DVSEC_REVID, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
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.cap = 0x26, /* 68B, IO, Mem, non-MLD */
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.ctrl = 0x02, /* IO always enabled */
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.status = 0x26, /* same as capabilities */
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.rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */
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};
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cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
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PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0,
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PCIE_FLEXBUS_PORT_DVSEC,
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PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec);
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}
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static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
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{
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ComponentRegisters *cregs = &ct3d->cxl_cstate.crb;
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uint32_t *cache_mem = cregs->cache_mem_registers;
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assert(which == 0);
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/* TODO: Sanity checks that the decoder is possible */
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ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
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ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
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ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
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}
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static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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CXLComponentState *cxl_cstate = opaque;
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ComponentRegisters *cregs = &cxl_cstate->crb;
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CXLType3Dev *ct3d = container_of(cxl_cstate, CXLType3Dev, cxl_cstate);
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uint32_t *cache_mem = cregs->cache_mem_registers;
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bool should_commit = false;
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int which_hdm = -1;
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assert(size == 4);
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g_assert(offset < CXL2_COMPONENT_CM_REGION_SIZE);
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switch (offset) {
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case A_CXL_HDM_DECODER0_CTRL:
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should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
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which_hdm = 0;
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break;
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default:
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break;
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}
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stl_le_p((uint8_t *)cache_mem + offset, value);
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if (should_commit) {
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hdm_decoder_commit(ct3d, which_hdm);
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}
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}
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static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
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{
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DeviceState *ds = DEVICE(ct3d);
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MemoryRegion *mr;
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char *name;
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if (!ct3d->hostmem) {
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error_setg(errp, "memdev property must be set");
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return false;
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}
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mr = host_memory_backend_get_memory(ct3d->hostmem);
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if (!mr) {
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error_setg(errp, "memdev property must be set");
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return false;
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}
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memory_region_set_nonvolatile(mr, true);
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memory_region_set_enabled(mr, true);
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host_memory_backend_set_mapped(ct3d->hostmem, true);
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if (ds->id) {
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name = g_strdup_printf("cxl-type3-dpa-space:%s", ds->id);
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} else {
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name = g_strdup("cxl-type3-dpa-space");
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}
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address_space_init(&ct3d->hostmem_as, mr, name);
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g_free(name);
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ct3d->cxl_dstate.pmem_size = ct3d->hostmem->size;
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if (!ct3d->lsa) {
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error_setg(errp, "lsa property must be set");
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return false;
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}
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return true;
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}
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static DOEProtocol doe_cdat_prot[] = {
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{ CXL_VENDOR_ID, CXL_DOE_TABLE_ACCESS, cxl_doe_cdat_rsp },
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{ }
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};
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static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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{
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CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
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CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
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ComponentRegisters *regs = &cxl_cstate->crb;
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MemoryRegion *mr = ®s->component_registers;
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uint8_t *pci_conf = pci_dev->config;
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unsigned short msix_num = 1;
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int i, rc;
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if (!cxl_setup_memory(ct3d, errp)) {
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return;
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}
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pci_config_set_prog_interface(pci_conf, 0x10);
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pcie_endpoint_cap_init(pci_dev, 0x80);
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if (ct3d->sn != UI64_NULL) {
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pcie_dev_ser_num_init(pci_dev, 0x100, ct3d->sn);
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cxl_cstate->dvsec_offset = 0x100 + 0x0c;
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} else {
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cxl_cstate->dvsec_offset = 0x100;
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}
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ct3d->cxl_cstate.pdev = pci_dev;
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build_dvsecs(ct3d);
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regs->special_ops = g_new0(MemoryRegionOps, 1);
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regs->special_ops->write = ct3d_reg_write;
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cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate,
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TYPE_CXL_TYPE3);
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pci_register_bar(
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pci_dev, CXL_COMPONENT_REG_BAR_IDX,
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PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, mr);
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cxl_device_register_block_init(OBJECT(pci_dev), &ct3d->cxl_dstate);
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pci_register_bar(pci_dev, CXL_DEVICE_REG_BAR_IDX,
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64,
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&ct3d->cxl_dstate.device_registers);
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/* MSI(-X) Initailization */
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rc = msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL);
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if (rc) {
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goto err_address_space_free;
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}
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for (i = 0; i < msix_num; i++) {
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msix_vector_use(pci_dev, i);
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}
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/* DOE Initailization */
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pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true, 0);
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cxl_cstate->cdat.build_cdat_table = ct3_build_cdat_table;
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cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table;
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cxl_cstate->cdat.private = ct3d;
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cxl_doe_cdat_init(cxl_cstate, errp);
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return;
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err_address_space_free:
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address_space_destroy(&ct3d->hostmem_as);
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return;
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}
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static void ct3_exit(PCIDevice *pci_dev)
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{
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CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
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CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
|
|
ComponentRegisters *regs = &cxl_cstate->crb;
|
|
|
|
cxl_doe_cdat_release(cxl_cstate);
|
|
g_free(regs->special_ops);
|
|
address_space_destroy(&ct3d->hostmem_as);
|
|
}
|
|
|
|
/* TODO: Support multiple HDM decoders and DPA skip */
|
|
static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa)
|
|
{
|
|
uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers;
|
|
uint64_t decoder_base, decoder_size, hpa_offset;
|
|
uint32_t hdm0_ctrl;
|
|
int ig, iw;
|
|
|
|
decoder_base = (((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI] << 32) |
|
|
cache_mem[R_CXL_HDM_DECODER0_BASE_LO]);
|
|
if ((uint64_t)host_addr < decoder_base) {
|
|
return false;
|
|
}
|
|
|
|
hpa_offset = (uint64_t)host_addr - decoder_base;
|
|
|
|
decoder_size = ((uint64_t)cache_mem[R_CXL_HDM_DECODER0_SIZE_HI] << 32) |
|
|
cache_mem[R_CXL_HDM_DECODER0_SIZE_LO];
|
|
if (hpa_offset >= decoder_size) {
|
|
return false;
|
|
}
|
|
|
|
hdm0_ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
|
|
iw = FIELD_EX32(hdm0_ctrl, CXL_HDM_DECODER0_CTRL, IW);
|
|
ig = FIELD_EX32(hdm0_ctrl, CXL_HDM_DECODER0_CTRL, IG);
|
|
|
|
*dpa = (MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
|
|
((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset) >> iw);
|
|
|
|
return true;
|
|
}
|
|
|
|
MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
|
|
unsigned size, MemTxAttrs attrs)
|
|
{
|
|
CXLType3Dev *ct3d = CXL_TYPE3(d);
|
|
uint64_t dpa_offset;
|
|
MemoryRegion *mr;
|
|
|
|
/* TODO support volatile region */
|
|
mr = host_memory_backend_get_memory(ct3d->hostmem);
|
|
if (!mr) {
|
|
return MEMTX_ERROR;
|
|
}
|
|
|
|
if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) {
|
|
return MEMTX_ERROR;
|
|
}
|
|
|
|
if (dpa_offset > int128_get64(mr->size)) {
|
|
return MEMTX_ERROR;
|
|
}
|
|
|
|
return address_space_read(&ct3d->hostmem_as, dpa_offset, attrs, data, size);
|
|
}
|
|
|
|
MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
|
|
unsigned size, MemTxAttrs attrs)
|
|
{
|
|
CXLType3Dev *ct3d = CXL_TYPE3(d);
|
|
uint64_t dpa_offset;
|
|
MemoryRegion *mr;
|
|
|
|
mr = host_memory_backend_get_memory(ct3d->hostmem);
|
|
if (!mr) {
|
|
return MEMTX_OK;
|
|
}
|
|
|
|
if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) {
|
|
return MEMTX_OK;
|
|
}
|
|
|
|
if (dpa_offset > int128_get64(mr->size)) {
|
|
return MEMTX_OK;
|
|
}
|
|
return address_space_write(&ct3d->hostmem_as, dpa_offset, attrs,
|
|
&data, size);
|
|
}
|
|
|
|
static void ct3d_reset(DeviceState *dev)
|
|
{
|
|
CXLType3Dev *ct3d = CXL_TYPE3(dev);
|
|
uint32_t *reg_state = ct3d->cxl_cstate.crb.cache_mem_registers;
|
|
uint32_t *write_msk = ct3d->cxl_cstate.crb.cache_mem_regs_write_mask;
|
|
|
|
cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE);
|
|
cxl_device_register_init_common(&ct3d->cxl_dstate);
|
|
}
|
|
|
|
static Property ct3_props[] = {
|
|
DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND,
|
|
HostMemoryBackend *),
|
|
DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
|
|
HostMemoryBackend *),
|
|
DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL),
|
|
DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static uint64_t get_lsa_size(CXLType3Dev *ct3d)
|
|
{
|
|
MemoryRegion *mr;
|
|
|
|
mr = host_memory_backend_get_memory(ct3d->lsa);
|
|
return memory_region_size(mr);
|
|
}
|
|
|
|
static void validate_lsa_access(MemoryRegion *mr, uint64_t size,
|
|
uint64_t offset)
|
|
{
|
|
assert(offset + size <= memory_region_size(mr));
|
|
assert(offset + size > offset);
|
|
}
|
|
|
|
static uint64_t get_lsa(CXLType3Dev *ct3d, void *buf, uint64_t size,
|
|
uint64_t offset)
|
|
{
|
|
MemoryRegion *mr;
|
|
void *lsa;
|
|
|
|
mr = host_memory_backend_get_memory(ct3d->lsa);
|
|
validate_lsa_access(mr, size, offset);
|
|
|
|
lsa = memory_region_get_ram_ptr(mr) + offset;
|
|
memcpy(buf, lsa, size);
|
|
|
|
return size;
|
|
}
|
|
|
|
static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size,
|
|
uint64_t offset)
|
|
{
|
|
MemoryRegion *mr;
|
|
void *lsa;
|
|
|
|
mr = host_memory_backend_get_memory(ct3d->lsa);
|
|
validate_lsa_access(mr, size, offset);
|
|
|
|
lsa = memory_region_get_ram_ptr(mr) + offset;
|
|
memcpy(lsa, buf, size);
|
|
memory_region_set_dirty(mr, offset, size);
|
|
|
|
/*
|
|
* Just like the PMEM, if the guest is not allowed to exit gracefully, label
|
|
* updates will get lost.
|
|
*/
|
|
}
|
|
|
|
static void ct3_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
|
|
CXLType3Class *cvc = CXL_TYPE3_CLASS(oc);
|
|
|
|
pc->realize = ct3_realize;
|
|
pc->exit = ct3_exit;
|
|
pc->class_id = PCI_CLASS_MEMORY_CXL;
|
|
pc->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
pc->device_id = 0xd93; /* LVF for now */
|
|
pc->revision = 1;
|
|
|
|
pc->config_write = ct3d_config_write;
|
|
pc->config_read = ct3d_config_read;
|
|
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
dc->desc = "CXL PMEM Device (Type 3)";
|
|
dc->reset = ct3d_reset;
|
|
device_class_set_props(dc, ct3_props);
|
|
|
|
cvc->get_lsa_size = get_lsa_size;
|
|
cvc->get_lsa = get_lsa;
|
|
cvc->set_lsa = set_lsa;
|
|
}
|
|
|
|
static const TypeInfo ct3d_info = {
|
|
.name = TYPE_CXL_TYPE3,
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.class_size = sizeof(struct CXLType3Class),
|
|
.class_init = ct3_class_init,
|
|
.instance_size = sizeof(CXLType3Dev),
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CXL_DEVICE },
|
|
{ INTERFACE_PCIE_DEVICE },
|
|
{}
|
|
},
|
|
};
|
|
|
|
static void ct3d_registers(void)
|
|
{
|
|
type_register_static(&ct3d_info);
|
|
}
|
|
|
|
type_init(ct3d_registers);
|