908 lines
30 KiB
C
908 lines
30 KiB
C
/*
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* Allwinner (sun4i and above) SD Host Controller emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "sysemu/blockdev.h"
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#include "sysemu/dma.h"
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#include "hw/qdev-properties.h"
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#include "hw/irq.h"
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#include "hw/sd/allwinner-sdhost.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#include "qom/object.h"
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#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
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/* This is reusing the SDBus typedef from SD_BUS */
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DECLARE_INSTANCE_CHECKER(SDBus, AW_SDHOST_BUS,
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TYPE_AW_SDHOST_BUS)
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/* SD Host register offsets */
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enum {
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REG_SD_GCTL = 0x00, /* Global Control */
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REG_SD_CKCR = 0x04, /* Clock Control */
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REG_SD_TMOR = 0x08, /* Timeout */
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REG_SD_BWDR = 0x0C, /* Bus Width */
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REG_SD_BKSR = 0x10, /* Block Size */
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REG_SD_BYCR = 0x14, /* Byte Count */
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REG_SD_CMDR = 0x18, /* Command */
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REG_SD_CAGR = 0x1C, /* Command Argument */
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REG_SD_RESP0 = 0x20, /* Response Zero */
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REG_SD_RESP1 = 0x24, /* Response One */
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REG_SD_RESP2 = 0x28, /* Response Two */
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REG_SD_RESP3 = 0x2C, /* Response Three */
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REG_SD_IMKR = 0x30, /* Interrupt Mask */
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REG_SD_MISR = 0x34, /* Masked Interrupt Status */
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REG_SD_RISR = 0x38, /* Raw Interrupt Status */
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REG_SD_STAR = 0x3C, /* Status */
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REG_SD_FWLR = 0x40, /* FIFO Water Level */
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REG_SD_FUNS = 0x44, /* FIFO Function Select */
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REG_SD_DBGC = 0x50, /* Debug Enable */
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REG_SD_A12A = 0x58, /* Auto command 12 argument */
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REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
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REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
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REG_SD_HWRST = 0x78, /* Hardware Reset Register */
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REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
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REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
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REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
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REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
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REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
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REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
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REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
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REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
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REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
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REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
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REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
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REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
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REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
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REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
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REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
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REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
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REG_SD_FIFO = 0x200, /* Read/Write FIFO */
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};
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/* SD Host register flags */
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enum {
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SD_GCTL_FIFO_AC_MOD = (1 << 31),
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SD_GCTL_DDR_MOD_SEL = (1 << 10),
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SD_GCTL_CD_DBC_ENB = (1 << 8),
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SD_GCTL_DMA_ENB = (1 << 5),
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SD_GCTL_INT_ENB = (1 << 4),
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SD_GCTL_DMA_RST = (1 << 2),
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SD_GCTL_FIFO_RST = (1 << 1),
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SD_GCTL_SOFT_RST = (1 << 0),
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};
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enum {
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SD_CMDR_LOAD = (1 << 31),
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SD_CMDR_CLKCHANGE = (1 << 21),
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SD_CMDR_WRITE = (1 << 10),
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SD_CMDR_AUTOSTOP = (1 << 12),
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SD_CMDR_DATA = (1 << 9),
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SD_CMDR_RESPONSE_LONG = (1 << 7),
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SD_CMDR_RESPONSE = (1 << 6),
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SD_CMDR_CMDID_MASK = (0x3f),
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};
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enum {
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SD_RISR_CARD_REMOVE = (1 << 31),
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SD_RISR_CARD_INSERT = (1 << 30),
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SD_RISR_SDIO_INTR = (1 << 16),
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SD_RISR_AUTOCMD_DONE = (1 << 14),
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SD_RISR_DATA_COMPLETE = (1 << 3),
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SD_RISR_CMD_COMPLETE = (1 << 2),
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SD_RISR_NO_RESPONSE = (1 << 1),
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};
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enum {
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SD_STAR_FIFO_EMPTY = (1 << 2),
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SD_STAR_CARD_PRESENT = (1 << 8),
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SD_STAR_FIFO_LEVEL_1 = (1 << 17),
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};
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enum {
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SD_IDST_INT_SUMMARY = (1 << 8),
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SD_IDST_RECEIVE_IRQ = (1 << 1),
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SD_IDST_TRANSMIT_IRQ = (1 << 0),
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SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
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SD_IDST_WR_MASK = (0x3ff),
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};
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/* SD Host register reset values */
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enum {
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REG_SD_GCTL_RST = 0x00000300,
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REG_SD_CKCR_RST = 0x0,
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REG_SD_TMOR_RST = 0xFFFFFF40,
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REG_SD_BWDR_RST = 0x0,
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REG_SD_BKSR_RST = 0x00000200,
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REG_SD_BYCR_RST = 0x00000200,
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REG_SD_CMDR_RST = 0x0,
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REG_SD_CAGR_RST = 0x0,
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REG_SD_RESP_RST = 0x0,
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REG_SD_IMKR_RST = 0x0,
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REG_SD_MISR_RST = 0x0,
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REG_SD_RISR_RST = 0x0,
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REG_SD_STAR_RST = 0x00000100,
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REG_SD_FWLR_RST = 0x000F0000,
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REG_SD_FUNS_RST = 0x0,
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REG_SD_DBGC_RST = 0x0,
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REG_SD_A12A_RST = 0x0000FFFF,
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REG_SD_NTSR_RST = 0x00000001,
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REG_SD_SDBG_RST = 0x0,
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REG_SD_HWRST_RST = 0x00000001,
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REG_SD_DMAC_RST = 0x0,
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REG_SD_DLBA_RST = 0x0,
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REG_SD_IDST_RST = 0x0,
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REG_SD_IDIE_RST = 0x0,
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REG_SD_THLDC_RST = 0x0,
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REG_SD_DSBD_RST = 0x0,
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REG_SD_RES_CRC_RST = 0x0,
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REG_SD_DATA_CRC_RST = 0x0,
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REG_SD_CRC_STA_RST = 0x0,
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REG_SD_FIFO_RST = 0x0,
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};
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/* Data transfer descriptor for DMA */
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typedef struct TransferDescriptor {
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uint32_t status; /* Status flags */
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uint32_t size; /* Data buffer size */
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uint32_t addr; /* Data buffer address */
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uint32_t next; /* Physical address of next descriptor */
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} TransferDescriptor;
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/* Data transfer descriptor flags */
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enum {
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DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
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DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
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DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
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DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
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DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
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DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
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DESC_SIZE_MASK = (0xfffffffc)
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};
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static void allwinner_sdhost_update_irq(AwSdHostState *s)
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{
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uint32_t irq;
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if (s->global_ctl & SD_GCTL_INT_ENB) {
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irq = s->irq_status & s->irq_mask;
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} else {
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irq = 0;
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}
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trace_allwinner_sdhost_update_irq(irq);
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qemu_set_irq(s->irq, irq);
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}
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static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
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uint32_t bytes)
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{
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if (s->transfer_cnt > bytes) {
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s->transfer_cnt -= bytes;
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} else {
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s->transfer_cnt = 0;
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}
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if (!s->transfer_cnt) {
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s->irq_status |= SD_RISR_DATA_COMPLETE;
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}
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}
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static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
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{
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AwSdHostState *s = AW_SDHOST(dev);
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trace_allwinner_sdhost_set_inserted(inserted);
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if (inserted) {
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s->irq_status |= SD_RISR_CARD_INSERT;
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s->irq_status &= ~SD_RISR_CARD_REMOVE;
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s->status |= SD_STAR_CARD_PRESENT;
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} else {
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s->irq_status &= ~SD_RISR_CARD_INSERT;
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s->irq_status |= SD_RISR_CARD_REMOVE;
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s->status &= ~SD_STAR_CARD_PRESENT;
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}
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allwinner_sdhost_update_irq(s);
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}
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static void allwinner_sdhost_send_command(AwSdHostState *s)
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{
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SDRequest request;
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uint8_t resp[16];
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int rlen;
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/* Auto clear load flag */
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s->command &= ~SD_CMDR_LOAD;
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/* Clock change does not actually interact with the SD bus */
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if (!(s->command & SD_CMDR_CLKCHANGE)) {
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/* Prepare request */
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request.cmd = s->command & SD_CMDR_CMDID_MASK;
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request.arg = s->command_arg;
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/* Send request to SD bus */
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rlen = sdbus_do_command(&s->sdbus, &request, resp);
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if (rlen < 0) {
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goto error;
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}
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/* If the command has a response, store it in the response registers */
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if ((s->command & SD_CMDR_RESPONSE)) {
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if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
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s->response[0] = ldl_be_p(&resp[0]);
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s->response[1] = s->response[2] = s->response[3] = 0;
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} else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
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s->response[0] = ldl_be_p(&resp[12]);
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s->response[1] = ldl_be_p(&resp[8]);
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s->response[2] = ldl_be_p(&resp[4]);
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s->response[3] = ldl_be_p(&resp[0]);
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} else {
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goto error;
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}
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}
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}
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/* Set interrupt status bits */
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s->irq_status |= SD_RISR_CMD_COMPLETE;
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return;
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error:
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s->irq_status |= SD_RISR_NO_RESPONSE;
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}
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static void allwinner_sdhost_auto_stop(AwSdHostState *s)
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{
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/*
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* The stop command (CMD12) ensures the SD bus
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* returns to the transfer state.
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*/
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if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
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/* First save current command registers */
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uint32_t saved_cmd = s->command;
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uint32_t saved_arg = s->command_arg;
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/* Prepare stop command (CMD12) */
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s->command &= ~SD_CMDR_CMDID_MASK;
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s->command |= 12; /* CMD12 */
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s->command_arg = 0;
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/* Put the command on SD bus */
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allwinner_sdhost_send_command(s);
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/* Restore command values */
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s->command = saved_cmd;
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s->command_arg = saved_arg;
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/* Set IRQ status bit for automatic stop done */
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s->irq_status |= SD_RISR_AUTOCMD_DONE;
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}
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}
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static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
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hwaddr desc_addr,
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TransferDescriptor *desc,
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bool is_write, uint32_t max_bytes)
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{
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AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
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uint32_t num_done = 0;
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uint32_t num_bytes = max_bytes;
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uint8_t buf[1024];
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/* Read descriptor */
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dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc),
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MEMTXATTRS_UNSPECIFIED);
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if (desc->size == 0) {
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desc->size = klass->max_desc_size;
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} else if (desc->size > klass->max_desc_size) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
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" is out-of-bounds: %" PRIu32 " > %zu",
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__func__, desc->size, klass->max_desc_size);
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desc->size = klass->max_desc_size;
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}
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if (desc->size < num_bytes) {
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num_bytes = desc->size;
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}
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trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
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is_write, max_bytes);
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while (num_done < num_bytes) {
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/* Try to completely fill the local buffer */
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uint32_t buf_bytes = num_bytes - num_done;
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if (buf_bytes > sizeof(buf)) {
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buf_bytes = sizeof(buf);
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}
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/* Write to SD bus */
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if (is_write) {
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dma_memory_read(&s->dma_as,
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(desc->addr & DESC_SIZE_MASK) + num_done, buf,
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buf_bytes, MEMTXATTRS_UNSPECIFIED);
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sdbus_write_data(&s->sdbus, buf, buf_bytes);
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/* Read from SD bus */
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} else {
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sdbus_read_data(&s->sdbus, buf, buf_bytes);
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dma_memory_write(&s->dma_as,
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(desc->addr & DESC_SIZE_MASK) + num_done, buf,
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buf_bytes, MEMTXATTRS_UNSPECIFIED);
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}
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num_done += buf_bytes;
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}
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/* Clear hold flag and flush descriptor */
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desc->status &= ~DESC_STATUS_HOLD;
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dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc),
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MEMTXATTRS_UNSPECIFIED);
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return num_done;
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}
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static void allwinner_sdhost_dma(AwSdHostState *s)
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{
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TransferDescriptor desc;
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hwaddr desc_addr = s->desc_base;
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bool is_write = (s->command & SD_CMDR_WRITE);
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uint32_t bytes_done = 0;
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/* Check if DMA can be performed */
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if (s->byte_count == 0 || s->block_size == 0 ||
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!(s->global_ctl & SD_GCTL_DMA_ENB)) {
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return;
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}
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/*
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* For read operations, data must be available on the SD bus
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* If not, it is an error and we should not act at all
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*/
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if (!is_write && !sdbus_data_ready(&s->sdbus)) {
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return;
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}
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/* Process the DMA descriptors until all data is copied */
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while (s->byte_count > 0) {
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bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
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is_write, s->byte_count);
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allwinner_sdhost_update_transfer_cnt(s, bytes_done);
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if (bytes_done <= s->byte_count) {
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s->byte_count -= bytes_done;
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} else {
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s->byte_count = 0;
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}
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if (desc.status & DESC_STATUS_LAST) {
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break;
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} else {
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desc_addr = desc.next;
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}
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}
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/* Raise IRQ to signal DMA is completed */
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s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
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/* Update DMAC bits */
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s->dmac_status |= SD_IDST_INT_SUMMARY;
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if (is_write) {
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s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
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} else {
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s->dmac_status |= SD_IDST_RECEIVE_IRQ;
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}
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}
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static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
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{
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uint32_t res = 0;
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if (sdbus_data_ready(&s->sdbus)) {
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sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
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le32_to_cpus(&res);
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allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
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allwinner_sdhost_auto_stop(s);
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allwinner_sdhost_update_irq(s);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
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__func__);
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}
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return res;
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}
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static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AwSdHostState *s = AW_SDHOST(opaque);
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AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
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uint32_t res = 0;
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switch (offset) {
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case REG_SD_GCTL: /* Global Control */
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res = s->global_ctl;
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break;
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case REG_SD_CKCR: /* Clock Control */
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res = s->clock_ctl;
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break;
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case REG_SD_TMOR: /* Timeout */
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res = s->timeout;
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break;
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case REG_SD_BWDR: /* Bus Width */
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res = s->bus_width;
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break;
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case REG_SD_BKSR: /* Block Size */
|
|
res = s->block_size;
|
|
break;
|
|
case REG_SD_BYCR: /* Byte Count */
|
|
res = s->byte_count;
|
|
break;
|
|
case REG_SD_CMDR: /* Command */
|
|
res = s->command;
|
|
break;
|
|
case REG_SD_CAGR: /* Command Argument */
|
|
res = s->command_arg;
|
|
break;
|
|
case REG_SD_RESP0: /* Response Zero */
|
|
res = s->response[0];
|
|
break;
|
|
case REG_SD_RESP1: /* Response One */
|
|
res = s->response[1];
|
|
break;
|
|
case REG_SD_RESP2: /* Response Two */
|
|
res = s->response[2];
|
|
break;
|
|
case REG_SD_RESP3: /* Response Three */
|
|
res = s->response[3];
|
|
break;
|
|
case REG_SD_IMKR: /* Interrupt Mask */
|
|
res = s->irq_mask;
|
|
break;
|
|
case REG_SD_MISR: /* Masked Interrupt Status */
|
|
res = s->irq_status & s->irq_mask;
|
|
break;
|
|
case REG_SD_RISR: /* Raw Interrupt Status */
|
|
res = s->irq_status;
|
|
break;
|
|
case REG_SD_STAR: /* Status */
|
|
res = s->status;
|
|
if (sdbus_data_ready(&s->sdbus)) {
|
|
res |= SD_STAR_FIFO_LEVEL_1;
|
|
} else {
|
|
res |= SD_STAR_FIFO_EMPTY;
|
|
}
|
|
break;
|
|
case REG_SD_FWLR: /* FIFO Water Level */
|
|
res = s->fifo_wlevel;
|
|
break;
|
|
case REG_SD_FUNS: /* FIFO Function Select */
|
|
res = s->fifo_func_sel;
|
|
break;
|
|
case REG_SD_DBGC: /* Debug Enable */
|
|
res = s->debug_enable;
|
|
break;
|
|
case REG_SD_A12A: /* Auto command 12 argument */
|
|
res = s->auto12_arg;
|
|
break;
|
|
case REG_SD_NTSR: /* SD NewTiming Set */
|
|
res = s->newtiming_set;
|
|
break;
|
|
case REG_SD_SDBG: /* SD newTiming Set Debug */
|
|
res = s->newtiming_debug;
|
|
break;
|
|
case REG_SD_HWRST: /* Hardware Reset Register */
|
|
res = s->hardware_rst;
|
|
break;
|
|
case REG_SD_DMAC: /* Internal DMA Controller Control */
|
|
res = s->dmac;
|
|
break;
|
|
case REG_SD_DLBA: /* Descriptor List Base Address */
|
|
res = s->desc_base;
|
|
break;
|
|
case REG_SD_IDST: /* Internal DMA Controller Status */
|
|
res = s->dmac_status;
|
|
break;
|
|
case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
|
|
res = s->dmac_irq;
|
|
break;
|
|
case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
|
|
if (sc->is_sun4i) {
|
|
res = allwinner_sdhost_fifo_read(s);
|
|
} else {
|
|
res = s->card_threshold;
|
|
}
|
|
break;
|
|
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
|
|
res = s->startbit_detect;
|
|
break;
|
|
case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
|
|
res = s->response_crc;
|
|
break;
|
|
case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
|
|
case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
|
|
case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
|
|
case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
|
|
case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
|
|
case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
|
|
case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
|
|
case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
|
|
res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
|
|
break;
|
|
case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
|
|
res = s->status_crc;
|
|
break;
|
|
case REG_SD_FIFO: /* Read/Write FIFO */
|
|
res = allwinner_sdhost_fifo_read(s);
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
|
|
HWADDR_PRIx"\n", __func__, offset);
|
|
res = 0;
|
|
break;
|
|
}
|
|
|
|
trace_allwinner_sdhost_read(offset, res, size);
|
|
return res;
|
|
}
|
|
|
|
static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
|
|
{
|
|
uint32_t u32 = cpu_to_le32(value);
|
|
sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
|
|
allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
|
|
allwinner_sdhost_auto_stop(s);
|
|
allwinner_sdhost_update_irq(s);
|
|
}
|
|
|
|
static void allwinner_sdhost_write(void *opaque, hwaddr offset,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
AwSdHostState *s = AW_SDHOST(opaque);
|
|
AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
|
|
|
|
trace_allwinner_sdhost_write(offset, value, size);
|
|
|
|
switch (offset) {
|
|
case REG_SD_GCTL: /* Global Control */
|
|
s->global_ctl = value;
|
|
s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
|
|
SD_GCTL_SOFT_RST);
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_CKCR: /* Clock Control */
|
|
s->clock_ctl = value;
|
|
break;
|
|
case REG_SD_TMOR: /* Timeout */
|
|
s->timeout = value;
|
|
break;
|
|
case REG_SD_BWDR: /* Bus Width */
|
|
s->bus_width = value;
|
|
break;
|
|
case REG_SD_BKSR: /* Block Size */
|
|
s->block_size = value;
|
|
break;
|
|
case REG_SD_BYCR: /* Byte Count */
|
|
s->byte_count = value;
|
|
s->transfer_cnt = value;
|
|
break;
|
|
case REG_SD_CMDR: /* Command */
|
|
s->command = value;
|
|
if (value & SD_CMDR_LOAD) {
|
|
allwinner_sdhost_send_command(s);
|
|
allwinner_sdhost_dma(s);
|
|
allwinner_sdhost_auto_stop(s);
|
|
}
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_CAGR: /* Command Argument */
|
|
s->command_arg = value;
|
|
break;
|
|
case REG_SD_RESP0: /* Response Zero */
|
|
s->response[0] = value;
|
|
break;
|
|
case REG_SD_RESP1: /* Response One */
|
|
s->response[1] = value;
|
|
break;
|
|
case REG_SD_RESP2: /* Response Two */
|
|
s->response[2] = value;
|
|
break;
|
|
case REG_SD_RESP3: /* Response Three */
|
|
s->response[3] = value;
|
|
break;
|
|
case REG_SD_IMKR: /* Interrupt Mask */
|
|
s->irq_mask = value;
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_MISR: /* Masked Interrupt Status */
|
|
case REG_SD_RISR: /* Raw Interrupt Status */
|
|
s->irq_status &= ~value;
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_STAR: /* Status */
|
|
s->status &= ~value;
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_FWLR: /* FIFO Water Level */
|
|
s->fifo_wlevel = value;
|
|
break;
|
|
case REG_SD_FUNS: /* FIFO Function Select */
|
|
s->fifo_func_sel = value;
|
|
break;
|
|
case REG_SD_DBGC: /* Debug Enable */
|
|
s->debug_enable = value;
|
|
break;
|
|
case REG_SD_A12A: /* Auto command 12 argument */
|
|
s->auto12_arg = value;
|
|
break;
|
|
case REG_SD_NTSR: /* SD NewTiming Set */
|
|
s->newtiming_set = value;
|
|
break;
|
|
case REG_SD_SDBG: /* SD newTiming Set Debug */
|
|
s->newtiming_debug = value;
|
|
break;
|
|
case REG_SD_HWRST: /* Hardware Reset Register */
|
|
s->hardware_rst = value;
|
|
break;
|
|
case REG_SD_DMAC: /* Internal DMA Controller Control */
|
|
s->dmac = value;
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_DLBA: /* Descriptor List Base Address */
|
|
s->desc_base = value;
|
|
break;
|
|
case REG_SD_IDST: /* Internal DMA Controller Status */
|
|
s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
|
|
s->dmac_irq = value;
|
|
allwinner_sdhost_update_irq(s);
|
|
break;
|
|
case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
|
|
if (sc->is_sun4i) {
|
|
allwinner_sdhost_fifo_write(s, value);
|
|
} else {
|
|
s->card_threshold = value;
|
|
}
|
|
break;
|
|
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
|
|
s->startbit_detect = value;
|
|
break;
|
|
case REG_SD_FIFO: /* Read/Write FIFO */
|
|
allwinner_sdhost_fifo_write(s, value);
|
|
break;
|
|
case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
|
|
case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
|
|
case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
|
|
case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
|
|
case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
|
|
case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
|
|
case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
|
|
case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
|
|
case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
|
|
case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
|
|
HWADDR_PRIx"\n", __func__, offset);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps allwinner_sdhost_ops = {
|
|
.read = allwinner_sdhost_read,
|
|
.write = allwinner_sdhost_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
.impl.min_access_size = 4,
|
|
};
|
|
|
|
static const VMStateDescription vmstate_allwinner_sdhost = {
|
|
.name = "allwinner-sdhost",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(global_ctl, AwSdHostState),
|
|
VMSTATE_UINT32(clock_ctl, AwSdHostState),
|
|
VMSTATE_UINT32(timeout, AwSdHostState),
|
|
VMSTATE_UINT32(bus_width, AwSdHostState),
|
|
VMSTATE_UINT32(block_size, AwSdHostState),
|
|
VMSTATE_UINT32(byte_count, AwSdHostState),
|
|
VMSTATE_UINT32(transfer_cnt, AwSdHostState),
|
|
VMSTATE_UINT32(command, AwSdHostState),
|
|
VMSTATE_UINT32(command_arg, AwSdHostState),
|
|
VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
|
|
VMSTATE_UINT32(irq_mask, AwSdHostState),
|
|
VMSTATE_UINT32(irq_status, AwSdHostState),
|
|
VMSTATE_UINT32(status, AwSdHostState),
|
|
VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
|
|
VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
|
|
VMSTATE_UINT32(debug_enable, AwSdHostState),
|
|
VMSTATE_UINT32(auto12_arg, AwSdHostState),
|
|
VMSTATE_UINT32(newtiming_set, AwSdHostState),
|
|
VMSTATE_UINT32(newtiming_debug, AwSdHostState),
|
|
VMSTATE_UINT32(hardware_rst, AwSdHostState),
|
|
VMSTATE_UINT32(dmac, AwSdHostState),
|
|
VMSTATE_UINT32(desc_base, AwSdHostState),
|
|
VMSTATE_UINT32(dmac_status, AwSdHostState),
|
|
VMSTATE_UINT32(dmac_irq, AwSdHostState),
|
|
VMSTATE_UINT32(card_threshold, AwSdHostState),
|
|
VMSTATE_UINT32(startbit_detect, AwSdHostState),
|
|
VMSTATE_UINT32(response_crc, AwSdHostState),
|
|
VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
|
|
VMSTATE_UINT32(status_crc, AwSdHostState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property allwinner_sdhost_properties[] = {
|
|
DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
|
|
TYPE_MEMORY_REGION, MemoryRegion *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void allwinner_sdhost_init(Object *obj)
|
|
{
|
|
AwSdHostState *s = AW_SDHOST(obj);
|
|
|
|
qbus_init(&s->sdbus, sizeof(s->sdbus),
|
|
TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
|
|
|
|
memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
|
|
TYPE_AW_SDHOST, 4 * KiB);
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
|
|
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
|
|
}
|
|
|
|
static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
AwSdHostState *s = AW_SDHOST(dev);
|
|
|
|
if (!s->dma_mr) {
|
|
error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
|
|
return;
|
|
}
|
|
|
|
address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
|
|
}
|
|
|
|
static void allwinner_sdhost_reset(DeviceState *dev)
|
|
{
|
|
AwSdHostState *s = AW_SDHOST(dev);
|
|
|
|
s->global_ctl = REG_SD_GCTL_RST;
|
|
s->clock_ctl = REG_SD_CKCR_RST;
|
|
s->timeout = REG_SD_TMOR_RST;
|
|
s->bus_width = REG_SD_BWDR_RST;
|
|
s->block_size = REG_SD_BKSR_RST;
|
|
s->byte_count = REG_SD_BYCR_RST;
|
|
s->transfer_cnt = 0;
|
|
|
|
s->command = REG_SD_CMDR_RST;
|
|
s->command_arg = REG_SD_CAGR_RST;
|
|
|
|
for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
|
|
s->response[i] = REG_SD_RESP_RST;
|
|
}
|
|
|
|
s->irq_mask = REG_SD_IMKR_RST;
|
|
s->irq_status = REG_SD_RISR_RST;
|
|
s->status = REG_SD_STAR_RST;
|
|
|
|
s->fifo_wlevel = REG_SD_FWLR_RST;
|
|
s->fifo_func_sel = REG_SD_FUNS_RST;
|
|
s->debug_enable = REG_SD_DBGC_RST;
|
|
s->auto12_arg = REG_SD_A12A_RST;
|
|
s->newtiming_set = REG_SD_NTSR_RST;
|
|
s->newtiming_debug = REG_SD_SDBG_RST;
|
|
s->hardware_rst = REG_SD_HWRST_RST;
|
|
s->dmac = REG_SD_DMAC_RST;
|
|
s->desc_base = REG_SD_DLBA_RST;
|
|
s->dmac_status = REG_SD_IDST_RST;
|
|
s->dmac_irq = REG_SD_IDIE_RST;
|
|
s->card_threshold = REG_SD_THLDC_RST;
|
|
s->startbit_detect = REG_SD_DSBD_RST;
|
|
s->response_crc = REG_SD_RES_CRC_RST;
|
|
|
|
for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
|
|
s->data_crc[i] = REG_SD_DATA_CRC_RST;
|
|
}
|
|
|
|
s->status_crc = REG_SD_CRC_STA_RST;
|
|
}
|
|
|
|
static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SDBusClass *sbc = SD_BUS_CLASS(klass);
|
|
|
|
sbc->set_inserted = allwinner_sdhost_set_inserted;
|
|
}
|
|
|
|
static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->reset = allwinner_sdhost_reset;
|
|
dc->vmsd = &vmstate_allwinner_sdhost;
|
|
dc->realize = allwinner_sdhost_realize;
|
|
device_class_set_props(dc, allwinner_sdhost_properties);
|
|
}
|
|
|
|
static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
|
|
sc->max_desc_size = 8 * KiB;
|
|
sc->is_sun4i = true;
|
|
}
|
|
|
|
static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
|
|
sc->max_desc_size = 64 * KiB;
|
|
sc->is_sun4i = false;
|
|
}
|
|
|
|
static const TypeInfo allwinner_sdhost_info = {
|
|
.name = TYPE_AW_SDHOST,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_init = allwinner_sdhost_init,
|
|
.instance_size = sizeof(AwSdHostState),
|
|
.class_init = allwinner_sdhost_class_init,
|
|
.class_size = sizeof(AwSdHostClass),
|
|
.abstract = true,
|
|
};
|
|
|
|
static const TypeInfo allwinner_sdhost_sun4i_info = {
|
|
.name = TYPE_AW_SDHOST_SUN4I,
|
|
.parent = TYPE_AW_SDHOST,
|
|
.class_init = allwinner_sdhost_sun4i_class_init,
|
|
};
|
|
|
|
static const TypeInfo allwinner_sdhost_sun5i_info = {
|
|
.name = TYPE_AW_SDHOST_SUN5I,
|
|
.parent = TYPE_AW_SDHOST,
|
|
.class_init = allwinner_sdhost_sun5i_class_init,
|
|
};
|
|
|
|
static const TypeInfo allwinner_sdhost_bus_info = {
|
|
.name = TYPE_AW_SDHOST_BUS,
|
|
.parent = TYPE_SD_BUS,
|
|
.instance_size = sizeof(SDBus),
|
|
.class_init = allwinner_sdhost_bus_class_init,
|
|
};
|
|
|
|
static void allwinner_sdhost_register_types(void)
|
|
{
|
|
type_register_static(&allwinner_sdhost_info);
|
|
type_register_static(&allwinner_sdhost_sun4i_info);
|
|
type_register_static(&allwinner_sdhost_sun5i_info);
|
|
type_register_static(&allwinner_sdhost_bus_info);
|
|
}
|
|
|
|
type_init(allwinner_sdhost_register_types)
|