222 lines
6.0 KiB
C
222 lines
6.0 KiB
C
/*
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* Nuvoton NPCM Peripheral SPI Module (PSPI)
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*
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* Copyright 2023 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/ssi/npcm_pspi.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "trace.h"
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REG16(PSPI_DATA, 0x0)
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REG16(PSPI_CTL1, 0x2)
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FIELD(PSPI_CTL1, SPIEN, 0, 1)
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FIELD(PSPI_CTL1, MOD, 2, 1)
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FIELD(PSPI_CTL1, EIR, 5, 1)
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FIELD(PSPI_CTL1, EIW, 6, 1)
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FIELD(PSPI_CTL1, SCM, 7, 1)
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FIELD(PSPI_CTL1, SCIDL, 8, 1)
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FIELD(PSPI_CTL1, SCDV, 9, 7)
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REG16(PSPI_STAT, 0x4)
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FIELD(PSPI_STAT, BSY, 0, 1)
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FIELD(PSPI_STAT, RBF, 1, 1)
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static void npcm_pspi_update_irq(NPCMPSPIState *s)
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{
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int level = 0;
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/* Only fire IRQ when the module is enabled. */
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if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
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/* Update interrupt as BSY is cleared. */
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if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
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FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
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level = 1;
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}
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/* Update interrupt as RBF is set. */
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if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
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FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
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level = 1;
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}
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}
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qemu_set_irq(s->irq, level);
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}
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static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
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{
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uint16_t value = s->regs[R_PSPI_DATA];
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/* Clear stat bits as the value are read out. */
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s->regs[R_PSPI_STAT] = 0;
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return value;
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}
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static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
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{
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uint16_t value = 0;
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if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
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value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
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}
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value |= ssi_transfer(s->spi, extract16(data, 0, 8));
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s->regs[R_PSPI_DATA] = value;
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/* Mark data as available */
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s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
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}
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/* Control register read handler. */
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static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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NPCMPSPIState *s = opaque;
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uint16_t value;
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switch (addr) {
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case A_PSPI_DATA:
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value = npcm_pspi_read_data(s);
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break;
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case A_PSPI_CTL1:
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value = s->regs[R_PSPI_CTL1];
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break;
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case A_PSPI_STAT:
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value = s->regs[R_PSPI_STAT];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to invalid offset 0x%" PRIx64 "\n",
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DEVICE(s)->canonical_path, addr);
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return 0;
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}
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trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
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npcm_pspi_update_irq(s);
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return value;
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}
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/* Control register write handler. */
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static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
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unsigned int size)
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{
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NPCMPSPIState *s = opaque;
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uint16_t value = v;
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trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
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switch (addr) {
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case A_PSPI_DATA:
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npcm_pspi_write_data(s, value);
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break;
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case A_PSPI_CTL1:
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s->regs[R_PSPI_CTL1] = value;
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break;
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case A_PSPI_STAT:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to read-only register PSPI_STAT: 0x%08"
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PRIx64 "\n", DEVICE(s)->canonical_path, v);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to invalid offset 0x%" PRIx64 "\n",
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DEVICE(s)->canonical_path, addr);
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return;
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}
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npcm_pspi_update_irq(s);
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}
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static const MemoryRegionOps npcm_pspi_ctrl_ops = {
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.read = npcm_pspi_ctrl_read,
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.write = npcm_pspi_ctrl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 2,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 2,
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.max_access_size = 2,
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.unaligned = false,
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},
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};
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static void npcm_pspi_enter_reset(Object *obj, ResetType type)
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{
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NPCMPSPIState *s = NPCM_PSPI(obj);
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trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
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memset(s->regs, 0, sizeof(s->regs));
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}
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static void npcm_pspi_realize(DeviceState *dev, Error **errp)
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{
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NPCMPSPIState *s = NPCM_PSPI(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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Object *obj = OBJECT(dev);
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s->spi = ssi_create_bus(dev, "pspi");
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memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
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"mmio", 4 * KiB);
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sysbus_init_mmio(sbd, &s->mmio);
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sysbus_init_irq(sbd, &s->irq);
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}
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static const VMStateDescription vmstate_npcm_pspi = {
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.name = "npcm-pspi",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void npcm_pspi_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "NPCM Peripheral SPI Module";
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dc->realize = npcm_pspi_realize;
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dc->vmsd = &vmstate_npcm_pspi;
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rc->phases.enter = npcm_pspi_enter_reset;
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}
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static const TypeInfo npcm_pspi_types[] = {
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{
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.name = TYPE_NPCM_PSPI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCMPSPIState),
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.class_init = npcm_pspi_class_init,
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},
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};
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DEFINE_TYPES(npcm_pspi_types);
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