310 lines
7.8 KiB
C++
310 lines
7.8 KiB
C++
/*
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* PMU register read/write functions for TCG IBM POWER chips
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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/*
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* Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the
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* PMCs) has problem state read access.
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*
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* Read acccess is granted for all PMCC values but 0b01, where a
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* Facility Unavailable Interrupt will occur.
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*/
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static bool spr_groupA_read_allowed(DisasContext *ctx)
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{
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if (!ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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return false;
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}
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return true;
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}
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/*
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* Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the
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* PMCs) has problem state write access.
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*
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* Write acccess is granted for PMCC values 0b10 and 0b11. Userspace
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* writing with PMCC 0b00 will generate a Hypervisor Emulation
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* Assistance Interrupt. Userspace writing with PMCC 0b01 will
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* generate a Facility Unavailable Interrupt.
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*/
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static bool spr_groupA_write_allowed(DisasContext *ctx)
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{
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if (ctx->mmcr0_pmcc0) {
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return true;
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}
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if (ctx->mmcr0_pmcc1) {
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/* PMCC = 0b01 */
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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} else {
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/* PMCC = 0b00 */
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gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
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}
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return false;
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}
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/*
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* Helper function to avoid code repetition between MMCR0 and
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* MMCR2 problem state write functions.
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*/
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static TCGv masked_gprn_for_spr_write(int gprn, int sprn,
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uint64_t spr_mask)
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{
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TCGv ret = tcg_temp_new();
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TCGv t0 = tcg_temp_new();
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/* 'ret' starts with all mask bits cleared */
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gen_load_spr(ret, sprn);
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tcg_gen_andi_tl(ret, ret, ~(spr_mask));
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/* Apply the mask into 'gprn' in a temp var */
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tcg_gen_andi_tl(t0, cpu_gpr[gprn], spr_mask);
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/* Add the masked gprn bits into 'ret' */
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tcg_gen_or_tl(ret, ret, t0);
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return ret;
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}
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void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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TCGv t0;
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if (!spr_groupA_read_allowed(ctx)) {
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return;
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}
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t0 = tcg_temp_new();
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/*
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* Filter out all bits but FC, PMAO, and PMAE, according
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* to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0,
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* fourth paragraph.
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*/
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gen_load_spr(t0, SPR_POWER_MMCR0);
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tcg_gen_andi_tl(t0, t0, MMCR0_UREG_MASK);
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tcg_gen_mov_tl(cpu_gpr[gprn], t0);
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}
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static void write_MMCR0_common(DisasContext *ctx, TCGv val)
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{
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/*
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* helper_store_mmcr0 will make clock based operations that
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* will cause 'bad icount read' errors if we do not execute
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* gen_icount_io_start() beforehand.
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*/
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gen_icount_io_start(ctx);
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gen_helper_store_mmcr0(cpu_env, val);
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/*
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* End the translation block because MMCR0 writes can change
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* ctx->pmu_insn_cnt.
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*/
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ctx->base.is_jmp = DISAS_EXIT_UPDATE;
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}
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void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv masked_gprn;
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if (!spr_groupA_write_allowed(ctx)) {
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return;
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}
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/*
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* Filter out all bits but FC, PMAO, and PMAE, according
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* to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0,
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* fourth paragraph.
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*/
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masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0,
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MMCR0_UREG_MASK);
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write_MMCR0_common(ctx, masked_gprn);
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}
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void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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TCGv t0;
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if (!spr_groupA_read_allowed(ctx)) {
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return;
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}
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t0 = tcg_temp_new();
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/*
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* On read, filter out all bits that are not FCnP0 bits.
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* When MMCR0[PMCC] is set to 0b10 or 0b11, providing
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* problem state programs read/write access to MMCR2,
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* only the FCnP0 bits can be accessed. All other bits are
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* not changed when mtspr is executed in problem state, and
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* all other bits return 0s when mfspr is executed in problem
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* state, according to ISA v3.1, section 10.4.6 Monitor Mode
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* Control Register 2, p. 1316, third paragraph.
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*/
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gen_load_spr(t0, SPR_POWER_MMCR2);
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tcg_gen_andi_tl(t0, t0, MMCR2_UREG_MASK);
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tcg_gen_mov_tl(cpu_gpr[gprn], t0);
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}
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void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv masked_gprn;
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if (!spr_groupA_write_allowed(ctx)) {
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return;
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}
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/*
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* Filter the bits that can be written using MMCR2_UREG_MASK,
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* similar to what is done in spr_write_MMCR0_ureg().
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*/
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masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR2,
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MMCR2_UREG_MASK);
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gen_store_spr(SPR_POWER_MMCR2, masked_gprn);
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}
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void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
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{
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TCGv_i32 t_sprn = tcg_const_i32(sprn);
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gen_icount_io_start(ctx);
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gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
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}
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void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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if (!spr_groupA_read_allowed(ctx)) {
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return;
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}
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spr_read_PMC(ctx, gprn, sprn + 0x10);
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}
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void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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/*
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* If PMCC = 0b11, PMC5 and PMC6 aren't included in the Performance
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* Monitor, and a read attempt results in a Facility Unavailable
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* Interrupt.
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*/
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if (ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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return;
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}
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/* The remaining steps are similar to PMCs 1-4 userspace read */
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spr_read_PMC14_ureg(ctx, gprn, sprn);
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}
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void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t_sprn = tcg_const_i32(sprn);
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gen_icount_io_start(ctx);
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gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
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}
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void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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if (!spr_groupA_write_allowed(ctx)) {
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return;
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}
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spr_write_PMC(ctx, sprn + 0x10, gprn);
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}
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void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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/*
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* If PMCC = 0b11, PMC5 and PMC6 aren't included in the Performance
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* Monitor, and a write attempt results in a Facility Unavailable
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* Interrupt.
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*/
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if (ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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return;
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}
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/* The remaining steps are similar to PMCs 1-4 userspace write */
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spr_write_PMC14_ureg(ctx, sprn, gprn);
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}
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void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
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{
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write_MMCR0_common(ctx, cpu_gpr[gprn]);
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}
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void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
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{
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gen_icount_io_start(ctx);
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gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]);
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}
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#else
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void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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spr_read_ureg(ctx, gprn, sprn);
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}
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void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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spr_noaccess(ctx, gprn, sprn);
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}
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void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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spr_read_ureg(ctx, gprn, sprn);
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}
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void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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spr_noaccess(ctx, gprn, sprn);
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}
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void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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spr_read_ureg(ctx, gprn, sprn);
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}
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void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
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{
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spr_read_ureg(ctx, gprn, sprn);
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}
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void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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spr_noaccess(ctx, gprn, sprn);
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}
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void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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spr_noaccess(ctx, gprn, sprn);
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}
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void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
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{
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spr_write_generic(ctx, sprn, gprn);
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}
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void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
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{
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spr_write_generic(ctx, sprn, gprn);
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}
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void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
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{
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spr_write_generic(ctx, sprn, gprn);
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}
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#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
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