454 lines
14 KiB
C
454 lines
14 KiB
C
/*
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* RISC-V PMU file.
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "pmu.h"
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#include "sysemu/cpu-timers.h"
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#include "sysemu/device_tree.h"
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#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
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#define MAKE_32BIT_MASK(shift, length) \
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(((uint32_t)(~0UL) >> (32 - (length))) << (shift))
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/*
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* To keep it simple, any event can be mapped to any programmable counters in
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* QEMU. The generic cycle & instruction count events can also be monitored
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* using programmable counters. In that case, mcycle & minstret must continue
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* to provide the correct value as well. Heterogeneous PMU per hart is not
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* supported yet. Thus, number of counters are same across all harts.
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*/
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void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
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{
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uint32_t fdt_event_ctr_map[20] = {};
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uint32_t cmask;
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/* All the programmable counters can map to any event */
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cmask = MAKE_32BIT_MASK(3, num_ctrs);
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/*
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* The event encoding is specified in the SBI specification
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* Event idx is a 20bits wide number encoded as follows:
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* event_idx[19:16] = type
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* event_idx[15:0] = code
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* The code field in cache events are encoded as follows:
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* event_idx.code[15:3] = cache_id
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* event_idx.code[2:1] = op_id
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* event_idx.code[0:0] = result_id
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*/
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/* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */
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fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);
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fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);
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fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);
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/* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */
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fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);
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fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
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fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
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/* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
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fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
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fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
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fdt_event_ctr_map[8] = cpu_to_be32(cmask);
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/* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
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fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
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fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
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fdt_event_ctr_map[11] = cpu_to_be32(cmask);
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/* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
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fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
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fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
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fdt_event_ctr_map[14] = cpu_to_be32(cmask);
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/* This a OpenSBI specific DT property documented in OpenSBI docs */
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qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters",
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fdt_event_ctr_map, sizeof(fdt_event_ctr_map));
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}
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static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
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{
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if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||
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!(cpu->pmu_avail_ctrs & BIT(ctr_idx))) {
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return false;
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} else {
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return true;
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}
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}
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static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx)
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{
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CPURISCVState *env = &cpu->env;
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if (riscv_pmu_counter_valid(cpu, ctr_idx) &&
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!get_field(env->mcountinhibit, BIT(ctr_idx))) {
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return true;
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} else {
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return false;
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}
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}
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static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
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{
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CPURISCVState *env = &cpu->env;
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target_ulong max_val = UINT32_MAX;
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PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
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bool virt_on = riscv_cpu_virt_enabled(env);
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/* Privilege mode filtering */
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if ((env->priv == PRV_M &&
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(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) ||
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(env->priv == PRV_S && virt_on &&
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(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) ||
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(env->priv == PRV_U && virt_on &&
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(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) ||
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(env->priv == PRV_S && !virt_on &&
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(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) ||
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(env->priv == PRV_U && !virt_on &&
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(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) {
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return 0;
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}
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/* Handle the overflow scenario */
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if (counter->mhpmcounter_val == max_val) {
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if (counter->mhpmcounterh_val == max_val) {
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counter->mhpmcounter_val = 0;
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counter->mhpmcounterh_val = 0;
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/* Generate interrupt only if OF bit is clear */
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if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
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env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
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riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
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}
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} else {
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counter->mhpmcounterh_val++;
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}
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} else {
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counter->mhpmcounter_val++;
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}
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return 0;
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}
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static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
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{
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CPURISCVState *env = &cpu->env;
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PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
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uint64_t max_val = UINT64_MAX;
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bool virt_on = riscv_cpu_virt_enabled(env);
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/* Privilege mode filtering */
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if ((env->priv == PRV_M &&
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(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) ||
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(env->priv == PRV_S && virt_on &&
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(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) ||
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(env->priv == PRV_U && virt_on &&
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(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) ||
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(env->priv == PRV_S && !virt_on &&
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(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) ||
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(env->priv == PRV_U && !virt_on &&
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(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) {
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return 0;
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}
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/* Handle the overflow scenario */
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if (counter->mhpmcounter_val == max_val) {
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counter->mhpmcounter_val = 0;
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/* Generate interrupt only if OF bit is clear */
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if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
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env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
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riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
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}
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} else {
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counter->mhpmcounter_val++;
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}
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return 0;
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}
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int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)
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{
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uint32_t ctr_idx;
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int ret;
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CPURISCVState *env = &cpu->env;
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gpointer value;
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if (!cpu->cfg.pmu_num) {
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return 0;
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}
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value = g_hash_table_lookup(cpu->pmu_event_ctr_map,
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GUINT_TO_POINTER(event_idx));
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if (!value) {
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return -1;
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}
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ctr_idx = GPOINTER_TO_UINT(value);
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if (!riscv_pmu_counter_enabled(cpu, ctr_idx) ||
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get_field(env->mcountinhibit, BIT(ctr_idx))) {
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return -1;
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}
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx);
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} else {
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ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx);
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}
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return ret;
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}
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bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
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uint32_t target_ctr)
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{
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RISCVCPU *cpu;
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uint32_t event_idx;
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uint32_t ctr_idx;
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/* Fixed instret counter */
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if (target_ctr == 2) {
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return true;
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}
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cpu = RISCV_CPU(env_cpu(env));
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if (!cpu->pmu_event_ctr_map) {
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return false;
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}
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event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS;
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ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
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GUINT_TO_POINTER(event_idx)));
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if (!ctr_idx) {
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return false;
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}
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return target_ctr == ctr_idx ? true : false;
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}
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bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
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{
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RISCVCPU *cpu;
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uint32_t event_idx;
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uint32_t ctr_idx;
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/* Fixed mcycle counter */
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if (target_ctr == 0) {
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return true;
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}
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cpu = RISCV_CPU(env_cpu(env));
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if (!cpu->pmu_event_ctr_map) {
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return false;
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}
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event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES;
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ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
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GUINT_TO_POINTER(event_idx)));
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/* Counter zero is not used for event_ctr_map */
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if (!ctr_idx) {
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return false;
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}
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return (target_ctr == ctr_idx) ? true : false;
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}
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static gboolean pmu_remove_event_map(gpointer key, gpointer value,
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gpointer udata)
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{
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return (GPOINTER_TO_UINT(value) == GPOINTER_TO_UINT(udata)) ? true : false;
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}
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static int64_t pmu_icount_ticks_to_ns(int64_t value)
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{
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int64_t ret = 0;
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if (icount_enabled()) {
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ret = icount_to_ns(value);
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} else {
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ret = (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value;
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}
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return ret;
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}
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int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
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uint32_t ctr_idx)
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{
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uint32_t event_idx;
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RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
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if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
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return -1;
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}
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/*
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* Expected mhpmevent value is zero for reset case. Remove the current
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* mapping.
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*/
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if (!value) {
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g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
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pmu_remove_event_map,
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GUINT_TO_POINTER(ctr_idx));
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return 0;
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}
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event_idx = value & MHPMEVENT_IDX_MASK;
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if (g_hash_table_lookup(cpu->pmu_event_ctr_map,
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GUINT_TO_POINTER(event_idx))) {
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return 0;
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}
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switch (event_idx) {
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case RISCV_PMU_EVENT_HW_CPU_CYCLES:
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case RISCV_PMU_EVENT_HW_INSTRUCTIONS:
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case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS:
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case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS:
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case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS:
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break;
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default:
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/* We don't support any raw events right now */
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return -1;
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}
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g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx),
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GUINT_TO_POINTER(ctr_idx));
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return 0;
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}
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static void pmu_timer_trigger_irq(RISCVCPU *cpu,
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enum riscv_pmu_event_idx evt_idx)
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{
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uint32_t ctr_idx;
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CPURISCVState *env = &cpu->env;
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PMUCTRState *counter;
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target_ulong *mhpmevent_val;
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uint64_t of_bit_mask;
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int64_t irq_trigger_at;
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if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES &&
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evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) {
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return;
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}
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ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,
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GUINT_TO_POINTER(evt_idx)));
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if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {
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return;
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}
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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mhpmevent_val = &env->mhpmeventh_val[ctr_idx];
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of_bit_mask = MHPMEVENTH_BIT_OF;
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} else {
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mhpmevent_val = &env->mhpmevent_val[ctr_idx];
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of_bit_mask = MHPMEVENT_BIT_OF;
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}
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counter = &env->pmu_ctrs[ctr_idx];
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if (counter->irq_overflow_left > 0) {
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irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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counter->irq_overflow_left;
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timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at);
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counter->irq_overflow_left = 0;
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return;
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}
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if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) {
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/* Generate interrupt only if OF bit is clear */
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if (!(*mhpmevent_val & of_bit_mask)) {
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*mhpmevent_val |= of_bit_mask;
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riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
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}
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}
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}
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/* Timer callback for instret and cycle counter overflow */
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void riscv_pmu_timer_cb(void *priv)
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{
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RISCVCPU *cpu = priv;
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/* Timer event was triggered only for these events */
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pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES);
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pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS);
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}
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int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
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{
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uint64_t overflow_delta, overflow_at;
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int64_t overflow_ns, overflow_left = 0;
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RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
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PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
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if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
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return -1;
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}
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if (value) {
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overflow_delta = UINT64_MAX - value + 1;
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} else {
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overflow_delta = UINT64_MAX;
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}
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/*
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* QEMU supports only int64_t timers while RISC-V counters are uint64_t.
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* Compute the leftover and save it so that it can be reprogrammed again
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* when timer expires.
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*/
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if (overflow_delta > INT64_MAX) {
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overflow_left = overflow_delta - INT64_MAX;
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}
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if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
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riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
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overflow_ns = pmu_icount_ticks_to_ns((int64_t)overflow_delta);
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overflow_left = pmu_icount_ticks_to_ns(overflow_left) ;
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} else {
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return -1;
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}
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overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
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if (overflow_at > INT64_MAX) {
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overflow_left += overflow_at - INT64_MAX;
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counter->irq_overflow_left = overflow_left;
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overflow_at = INT64_MAX;
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}
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timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
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return 0;
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}
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int riscv_pmu_init(RISCVCPU *cpu, int num_counters)
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{
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if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) {
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return -1;
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}
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cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal);
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if (!cpu->pmu_event_ctr_map) {
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/* PMU support can not be enabled */
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qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n");
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cpu->cfg.pmu_num = 0;
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return -1;
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}
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|
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/* Create a bitmask of available programmable counters */
|
|
cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, num_counters);
|
|
|
|
return 0;
|
|
}
|