343 lines
9.0 KiB
C
343 lines
9.0 KiB
C
/*
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* QEMU model of the Milkymist System Controller.
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*
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* Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.milkymist.org/socdoc/sysctl.pdf
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*/
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "trace.h"
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#include "qemu/timer.h"
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#include "hw/ptimer.h"
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#include "qemu/error-report.h"
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enum {
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CTRL_ENABLE = (1<<0),
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CTRL_AUTORESTART = (1<<1),
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};
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enum {
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ICAP_READY = (1<<0),
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};
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enum {
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R_GPIO_IN = 0,
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R_GPIO_OUT,
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R_GPIO_INTEN,
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R_TIMER0_CONTROL = 4,
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R_TIMER0_COMPARE,
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R_TIMER0_COUNTER,
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R_TIMER1_CONTROL = 8,
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R_TIMER1_COMPARE,
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R_TIMER1_COUNTER,
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R_ICAP = 16,
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R_DBG_SCRATCHPAD = 20,
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R_DBG_WRITE_LOCK,
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R_CLK_FREQUENCY = 29,
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R_CAPABILITIES,
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R_SYSTEM_ID,
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R_MAX
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};
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#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
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#define MILKYMIST_SYSCTL(obj) \
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OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
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struct MilkymistSysctlState {
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SysBusDevice parent_obj;
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MemoryRegion regs_region;
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QEMUBH *bh0;
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QEMUBH *bh1;
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ptimer_state *ptimer0;
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ptimer_state *ptimer1;
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uint32_t freq_hz;
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uint32_t capabilities;
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uint32_t systemid;
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uint32_t strappings;
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uint32_t regs[R_MAX];
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qemu_irq gpio_irq;
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qemu_irq timer0_irq;
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qemu_irq timer1_irq;
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};
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typedef struct MilkymistSysctlState MilkymistSysctlState;
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static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
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{
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trace_milkymist_sysctl_icap_write(value);
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switch (value & 0xffff) {
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case 0x000e:
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qemu_system_shutdown_request();
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break;
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}
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}
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static uint64_t sysctl_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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MilkymistSysctlState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_TIMER0_COUNTER:
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r = (uint32_t)ptimer_get_count(s->ptimer0);
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/* milkymist timer counts up */
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r = s->regs[R_TIMER0_COMPARE] - r;
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break;
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case R_TIMER1_COUNTER:
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r = (uint32_t)ptimer_get_count(s->ptimer1);
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/* milkymist timer counts up */
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r = s->regs[R_TIMER1_COMPARE] - r;
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break;
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case R_GPIO_IN:
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case R_GPIO_OUT:
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case R_GPIO_INTEN:
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case R_TIMER0_CONTROL:
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case R_TIMER0_COMPARE:
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case R_TIMER1_CONTROL:
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case R_TIMER1_COMPARE:
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case R_ICAP:
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case R_DBG_SCRATCHPAD:
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case R_DBG_WRITE_LOCK:
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case R_CLK_FREQUENCY:
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case R_CAPABILITIES:
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case R_SYSTEM_ID:
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r = s->regs[addr];
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break;
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default:
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error_report("milkymist_sysctl: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_milkymist_sysctl_memory_read(addr << 2, r);
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return r;
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}
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static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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MilkymistSysctlState *s = opaque;
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trace_milkymist_sysctl_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_GPIO_OUT:
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case R_GPIO_INTEN:
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case R_TIMER0_COUNTER:
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case R_TIMER1_COUNTER:
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case R_DBG_SCRATCHPAD:
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s->regs[addr] = value;
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break;
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case R_TIMER0_COMPARE:
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ptimer_set_limit(s->ptimer0, value, 0);
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s->regs[addr] = value;
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break;
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case R_TIMER1_COMPARE:
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ptimer_set_limit(s->ptimer1, value, 0);
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s->regs[addr] = value;
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break;
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case R_TIMER0_CONTROL:
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s->regs[addr] = value;
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if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
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trace_milkymist_sysctl_start_timer0();
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ptimer_set_count(s->ptimer0,
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s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
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ptimer_run(s->ptimer0, 0);
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} else {
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trace_milkymist_sysctl_stop_timer0();
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ptimer_stop(s->ptimer0);
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}
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break;
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case R_TIMER1_CONTROL:
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s->regs[addr] = value;
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if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
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trace_milkymist_sysctl_start_timer1();
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ptimer_set_count(s->ptimer1,
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s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
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ptimer_run(s->ptimer1, 0);
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} else {
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trace_milkymist_sysctl_stop_timer1();
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ptimer_stop(s->ptimer1);
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}
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break;
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case R_ICAP:
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sysctl_icap_write(s, value);
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break;
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case R_DBG_WRITE_LOCK:
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s->regs[addr] = 1;
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break;
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case R_SYSTEM_ID:
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qemu_system_reset_request();
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break;
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case R_GPIO_IN:
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case R_CLK_FREQUENCY:
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case R_CAPABILITIES:
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error_report("milkymist_sysctl: write to read-only register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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default:
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error_report("milkymist_sysctl: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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}
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static const MemoryRegionOps sysctl_mmio_ops = {
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.read = sysctl_read,
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.write = sysctl_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void timer0_hit(void *opaque)
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{
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MilkymistSysctlState *s = opaque;
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if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
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s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
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trace_milkymist_sysctl_stop_timer0();
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ptimer_stop(s->ptimer0);
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}
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trace_milkymist_sysctl_pulse_irq_timer0();
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qemu_irq_pulse(s->timer0_irq);
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}
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static void timer1_hit(void *opaque)
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{
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MilkymistSysctlState *s = opaque;
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if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
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s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
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trace_milkymist_sysctl_stop_timer1();
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ptimer_stop(s->ptimer1);
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}
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trace_milkymist_sysctl_pulse_irq_timer1();
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qemu_irq_pulse(s->timer1_irq);
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}
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static void milkymist_sysctl_reset(DeviceState *d)
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{
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MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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ptimer_stop(s->ptimer0);
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ptimer_stop(s->ptimer1);
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/* defaults */
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s->regs[R_ICAP] = ICAP_READY;
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s->regs[R_SYSTEM_ID] = s->systemid;
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s->regs[R_CLK_FREQUENCY] = s->freq_hz;
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s->regs[R_CAPABILITIES] = s->capabilities;
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s->regs[R_GPIO_IN] = s->strappings;
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}
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static int milkymist_sysctl_init(SysBusDevice *dev)
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{
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MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
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sysbus_init_irq(dev, &s->gpio_irq);
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sysbus_init_irq(dev, &s->timer0_irq);
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sysbus_init_irq(dev, &s->timer1_irq);
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s->bh0 = qemu_bh_new(timer0_hit, s);
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s->bh1 = qemu_bh_new(timer1_hit, s);
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s->ptimer0 = ptimer_init(s->bh0);
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s->ptimer1 = ptimer_init(s->bh1);
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ptimer_set_freq(s->ptimer0, s->freq_hz);
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ptimer_set_freq(s->ptimer1, s->freq_hz);
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memory_region_init_io(&s->regs_region, OBJECT(s), &sysctl_mmio_ops, s,
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"milkymist-sysctl", R_MAX * 4);
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sysbus_init_mmio(dev, &s->regs_region);
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return 0;
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}
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static const VMStateDescription vmstate_milkymist_sysctl = {
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.name = "milkymist-sysctl",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
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VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
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VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property milkymist_sysctl_properties[] = {
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DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
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freq_hz, 80000000),
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DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
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capabilities, 0x00000000),
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DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
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systemid, 0x10014d31),
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DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
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strappings, 0x00000001),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = milkymist_sysctl_init;
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dc->reset = milkymist_sysctl_reset;
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dc->vmsd = &vmstate_milkymist_sysctl;
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dc->props = milkymist_sysctl_properties;
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}
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static const TypeInfo milkymist_sysctl_info = {
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.name = TYPE_MILKYMIST_SYSCTL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MilkymistSysctlState),
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.class_init = milkymist_sysctl_class_init,
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};
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static void milkymist_sysctl_register_types(void)
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{
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type_register_static(&milkymist_sysctl_info);
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}
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type_init(milkymist_sysctl_register_types)
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