4c315c2766
Several devices don't survive object_unref(object_new(T)): they crash or hang during cleanup, or they leave dangling pointers behind. This breaks at least device-list-properties, because qmp_device_list_properties() needs to create a device to find its properties. Broken in commitf4eb32b
"qmp: show QOM properties in device-list-properties", v2.1. Example reproducer: $ qemu-system-aarch64 -nodefaults -display none -machine none -S -qmp stdio {"QMP": {"version": {"qemu": {"micro": 50, "minor": 4, "major": 2}, "package": ""}, "capabilities": []}} { "execute": "qmp_capabilities" } {"return": {}} { "execute": "device-list-properties", "arguments": { "typename": "pxa2xx-pcmcia" } } qemu-system-aarch64: /home/armbru/work/qemu/memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. Aborted (core dumped) [Exit 134 (SIGABRT)] Unfortunately, I can't fix the problems in these devices right now. Instead, add DeviceClass member cannot_destroy_with_object_finalize_yet to mark them: * Hang during cleanup (didn't debug, so I can't say why): "realview_pci", "versatile_pci". * Dangling pointer in cpus: most CPUs, plus "allwinner-a10", "digic", "fsl,imx25", "fsl,imx31", "xlnx,zynqmp", because they create such CPUs * Assert kvm_enabled(): "host-x86_64-cpu", host-i386-cpu", "host-powerpc64-cpu", "host-embedded-powerpc-cpu", "host-powerpc-cpu" (the powerpc ones can't currently reach the assertion, because the CPUs are only registered when KVM is enabled, but the assertion is arguably in the wrong place all the same) Make qmp_device_list_properties() fail cleanly when the device is so marked. This improves device-list-properties from "crashes, hangs or leaves dangling pointers behind" to "fails". Not a complete fix, just a better-than-nothing work-around. In the above reproducer, device-list-properties now fails with "Can't list properties of device 'pxa2xx-pcmcia'". This also protects -device FOO,help, which uses the same machinery since commitef52358
"qdev-monitor: include QOM properties in -device FOO, help output", v2.2. Example reproducer: $ qemu-system-aarch64 -machine none -device pxa2xx-pcmcia,help Before: qemu-system-aarch64: .../memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. After: Can't list properties of device 'pxa2xx-pcmcia' Cc: "Andreas Färber" <afaerber@suse.de> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Anthony Green <green@moxielogic.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Jia Liu <proljc@gmail.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Cc: qemu-ppc@nongnu.org Cc: qemu-stable@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1443689999-12182-10-git-send-email-armbru@redhat.com>
296 lines
10 KiB
C
296 lines
10 KiB
C
/*
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* Xilinx Zynq MPSoC emulation
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*
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* Copyright (C) 2015 Xilinx Inc
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "hw/arm/xlnx-zynqmp.h"
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#include "hw/intc/arm_gic_common.h"
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#include "exec/address-spaces.h"
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#define GIC_NUM_SPI_INTR 160
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#define ARM_PHYS_TIMER_PPI 30
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#define ARM_VIRT_TIMER_PPI 27
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#define GIC_BASE_ADDR 0xf9000000
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#define GIC_DIST_ADDR 0xf9010000
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#define GIC_CPU_ADDR 0xf9020000
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#define SATA_INTR 133
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#define SATA_ADDR 0xFD0C0000
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#define SATA_NUM_PORTS 2
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static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
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0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
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};
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static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
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57, 59, 61, 63,
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};
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static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
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0xFF000000, 0xFF010000,
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};
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static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
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21, 22,
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};
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typedef struct XlnxZynqMPGICRegion {
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int region_index;
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uint32_t address;
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} XlnxZynqMPGICRegion;
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static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
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{ .region_index = 0, .address = GIC_DIST_ADDR, },
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{ .region_index = 1, .address = GIC_CPU_ADDR, },
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};
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static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
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{
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return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
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}
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static void xlnx_zynqmp_init(Object *obj)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
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int i;
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for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
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object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
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"cortex-a53-" TYPE_ARM_CPU);
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object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
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&error_abort);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
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object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
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"cortex-r5-" TYPE_ARM_CPU);
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object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
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&error_abort);
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}
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object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
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qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
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for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
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object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
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qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
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object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
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qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
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}
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object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
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qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
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}
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static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
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MemoryRegion *system_memory = get_system_memory();
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uint8_t i;
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const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
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qemu_irq gic_spi[GIC_NUM_SPI_INTR];
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Error *err = NULL;
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/* Create the four OCM banks */
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for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
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char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
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memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
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XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
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vmstate_register_ram_global(&s->ocm_ram[i]);
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memory_region_add_subregion(get_system_memory(),
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XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
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i * XLNX_ZYNQMP_OCM_RAM_SIZE,
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&s->ocm_ram[i]);
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g_free(ocm_name);
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}
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
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object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
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for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
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SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
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const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
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MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
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uint32_t addr = r->address;
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int j;
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sysbus_mmio_map(gic, r->region_index, addr);
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for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
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MemoryRegion *alias = &s->gic_mr[i][j];
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addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
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memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
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0, XLNX_ZYNQMP_GIC_REGION_SIZE);
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memory_region_add_subregion(system_memory, addr, alias);
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}
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
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qemu_irq irq;
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char *name;
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object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
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"psci-conduit", &error_abort);
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name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
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if (strcmp(name, boot_cpu)) {
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/* Secondary CPUs start in PSCI powered-down state */
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object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
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"start-powered-off", &error_abort);
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} else {
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s->boot_cpu_ptr = &s->apu_cpu[i];
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}
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g_free(name);
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object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
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"reset-cbar", &error_abort);
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object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
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qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
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ARM_CPU_IRQ));
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irq = qdev_get_gpio_in(DEVICE(&s->gic),
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arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
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qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
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irq = qdev_get_gpio_in(DEVICE(&s->gic),
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arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
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qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
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char *name;
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name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
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if (strcmp(name, boot_cpu)) {
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/* Secondary CPUs start in PSCI powered-down state */
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
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"start-powered-off", &error_abort);
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} else {
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s->boot_cpu_ptr = &s->rpu_cpu[i];
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}
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g_free(name);
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
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&error_abort);
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object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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if (!s->boot_cpu_ptr) {
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error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu);
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return;
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}
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for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
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gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
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NICInfo *nd = &nd_table[i];
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if (nd->used) {
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qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
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qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
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}
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object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
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gic_spi[gem_intr[i]]);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
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object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
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gic_spi[uart_intr[i]]);
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}
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object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
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&error_abort);
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object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
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}
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static Property xlnx_zynqmp_props[] = {
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DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
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DEFINE_PROP_END_OF_LIST()
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};
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static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->props = xlnx_zynqmp_props;
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dc->realize = xlnx_zynqmp_realize;
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/*
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* Reason: creates an ARM CPU, thus use after free(), see
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* arm_cpu_class_init()
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*/
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dc->cannot_destroy_with_object_finalize_yet = true;
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}
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static const TypeInfo xlnx_zynqmp_type_info = {
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.name = TYPE_XLNX_ZYNQMP,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(XlnxZynqMPState),
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.instance_init = xlnx_zynqmp_init,
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.class_init = xlnx_zynqmp_class_init,
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};
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static void xlnx_zynqmp_register_types(void)
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{
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type_register_static(&xlnx_zynqmp_type_info);
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}
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type_init(xlnx_zynqmp_register_types)
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