316 lines
10 KiB
C
316 lines
10 KiB
C
/*
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* Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
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*
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* Copyright (c) 2010 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/datadir.h"
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#include "qemu/units.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/block/flash.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/reset.h"
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#include "hw/boards.h"
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#include "sysemu/device_tree.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/option.h"
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#include "hw/intc/ppc-uic.h"
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/ppc4xx.h"
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#include "hw/qdev-properties.h"
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#include "ppc405.h"
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#define EPAPR_MAGIC (0x45504150)
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#define FLASH_SIZE (16 * MiB)
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#define INTC_BASEADDR 0x81800000
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#define UART16550_BASEADDR 0x83e01003
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#define TIMER_BASEADDR 0x83c00000
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#define PFLASH_BASEADDR 0xfc000000
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#define TIMER_IRQ 3
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#define UART16550_IRQ 9
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static struct boot_info
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{
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uint32_t bootstrap_pc;
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uint32_t cmdline;
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uint32_t fdt;
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uint32_t ima_size;
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void *vfdt;
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} boot_info;
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/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
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static void mmubooke_create_initial_mapping(CPUPPCState *env,
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target_ulong va,
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hwaddr pa)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1U << 31; /* up to 0x80000000 */
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tlb->EPN = va & TARGET_PAGE_MASK;
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tlb->RPN = pa & TARGET_PAGE_MASK;
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tlb->PID = 0;
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tlb = &env->tlb.tlbe[1];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1U << 31; /* up to 0xffffffff */
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tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->PID = 0;
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}
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static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
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{
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PowerPCCPU *cpu;
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CPUPPCState *env;
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DeviceState *uicdev;
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SysBusDevice *uicsbd;
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cpu = POWERPC_CPU(cpu_create(cpu_type));
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env = &cpu->env;
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ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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uicdev = qdev_new(TYPE_PPC_UIC);
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uicsbd = SYS_BUS_DEVICE(uicdev);
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object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
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&error_fatal);
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sysbus_realize_and_unref(uicsbd, &error_fatal);
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sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
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qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
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sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
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qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
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/* This board doesn't wire anything up to the inputs of the UIC. */
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return cpu;
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}
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static void main_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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struct boot_info *bi = env->load_info;
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cpu_reset(CPU(cpu));
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/* Linux Kernel Parameters (passing device tree):
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* r3: pointer to the fdt
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* r4: 0
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* r5: 0
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* r6: epapr magic
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* r7: size of IMA in bytes
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* r8: 0
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* r9: 0
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*/
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env->gpr[1] = (16 * MiB) - 8;
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/* Provide a device-tree. */
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env->gpr[3] = bi->fdt;
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env->nip = bi->bootstrap_pc;
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/* Create a mapping for the kernel. */
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mmubooke_create_initial_mapping(env, 0, 0);
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env->gpr[6] = tswap32(EPAPR_MAGIC);
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env->gpr[7] = bi->ima_size;
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}
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#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
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static int xilinx_load_device_tree(hwaddr addr,
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uint32_t ramsize,
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hwaddr initrd_base,
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hwaddr initrd_size,
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const char *kernel_cmdline)
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{
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char *path;
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int fdt_size;
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void *fdt = NULL;
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int r;
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const char *dtb_filename;
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dtb_filename = current_machine->dtb;
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if (dtb_filename) {
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fdt = load_device_tree(dtb_filename, &fdt_size);
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if (!fdt) {
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error_report("Error while loading device tree file '%s'",
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dtb_filename);
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}
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} else {
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/* Try the local "ppc.dtb" override. */
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fdt = load_device_tree("ppc.dtb", &fdt_size);
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if (!fdt) {
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path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (path) {
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fdt = load_device_tree(path, &fdt_size);
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g_free(path);
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}
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}
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}
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if (!fdt) {
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return 0;
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}
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r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
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initrd_base);
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if (r < 0) {
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error_report("couldn't set /chosen/linux,initrd-start");
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}
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r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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if (r < 0) {
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error_report("couldn't set /chosen/linux,initrd-end");
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}
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r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
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if (r < 0)
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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cpu_physical_memory_write(addr, fdt, fdt_size);
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g_free(fdt);
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return fdt_size;
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}
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static void virtex_init(MachineState *machine)
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{
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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hwaddr initrd_base = 0;
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int initrd_size = 0;
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MemoryRegion *address_space_mem = get_system_memory();
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DeviceState *dev;
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PowerPCCPU *cpu;
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CPUPPCState *env;
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hwaddr ram_base = 0;
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DriveInfo *dinfo;
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qemu_irq irq[32], cpu_irq;
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int kernel_size;
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int i;
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/* init CPUs */
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cpu = ppc440_init_xilinx(machine->cpu_type, 400000000);
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env = &cpu->env;
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if (env->mmu_model != POWERPC_MMU_BOOKE) {
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error_report("MMU model %i not supported by this machine",
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env->mmu_model);
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exit(1);
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}
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qemu_register_reset(main_cpu_reset, cpu);
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memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
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dinfo = drive_get(IF_PFLASH, 0, 0);
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pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
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dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
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64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
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cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT);
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dev = qdev_new("xlnx.xps-intc");
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qdev_prop_set_uint32(dev, "kind-of-intr", 0);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(dev, i);
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}
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serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
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115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
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/* 2 timers at irq 2 @ 62 Mhz. */
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dev = qdev_new("xlnx.xps-timer");
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qdev_prop_set_uint32(dev, "one-timer-only", 0);
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qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
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if (kernel_filename) {
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uint64_t entry, high;
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hwaddr boot_offset;
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/* Boots a kernel elf binary. */
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kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
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&entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE,
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0, 0);
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boot_info.bootstrap_pc = entry & 0x00ffffff;
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if (kernel_size < 0) {
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boot_offset = 0x1200000;
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/* If we failed loading ELF's try a raw image. */
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kernel_size = load_image_targphys(kernel_filename,
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boot_offset,
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machine->ram_size);
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boot_info.bootstrap_pc = boot_offset;
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high = boot_info.bootstrap_pc + kernel_size + 8192;
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}
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boot_info.ima_size = kernel_size;
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/* Load initrd. */
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if (machine->initrd_filename) {
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initrd_base = high = ROUND_UP(high, 4);
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initrd_size = load_image_targphys(machine->initrd_filename,
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high, machine->ram_size - high);
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if (initrd_size < 0) {
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error_report("couldn't load ram disk '%s'",
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machine->initrd_filename);
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exit(1);
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}
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high = ROUND_UP(high + initrd_size, 4);
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}
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/* Provide a device-tree. */
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boot_info.fdt = high + (8192 * 2);
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boot_info.fdt &= ~8191;
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xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
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initrd_base, initrd_size,
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kernel_cmdline);
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}
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env->load_info = &boot_info;
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}
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static void virtex_machine_init(MachineClass *mc)
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{
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mc->desc = "Xilinx Virtex ML507 reference design";
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mc->init = virtex_init;
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
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mc->default_ram_id = "ram";
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}
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DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
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