40336d5b1d
This change adds support for inserting virtual interrupts from HS-mode into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering from HS-mode. Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows HS-mode to assert virtual interrupts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231016111736.28721-7-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
430 lines
12 KiB
C
430 lines
12 KiB
C
/*
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* RISC-V VMState Description
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*
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* Copyright (c) 2020 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "migration/cpu.h"
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#include "sysemu/cpu-timers.h"
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#include "debug.h"
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static bool pmp_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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return cpu->cfg.pmp;
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}
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static int pmp_post_load(void *opaque, int version_id)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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int i;
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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pmp_update_rule_addr(env, i);
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}
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pmp_update_rule_nums(env);
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return 0;
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}
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static const VMStateDescription vmstate_pmp_entry = {
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.name = "cpu/pmp/entry",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(addr_reg, pmp_entry_t),
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VMSTATE_UINT8(cfg_reg, pmp_entry_t),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pmp = {
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.name = "cpu/pmp",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pmp_needed,
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.post_load = pmp_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
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0, vmstate_pmp_entry, pmp_entry_t),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool hyper_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVH);
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}
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static const VMStateDescription vmstate_hyper = {
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.name = "cpu/hyper",
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.version_id = 3,
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.minimum_version_id = 3,
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.needed = hyper_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.hstatus, RISCVCPU),
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VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
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VMSTATE_UINT64(env.hideleg, RISCVCPU),
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VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
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VMSTATE_UINTTL(env.htval, RISCVCPU),
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VMSTATE_UINTTL(env.htinst, RISCVCPU),
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VMSTATE_UINTTL(env.hgatp, RISCVCPU),
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VMSTATE_UINTTL(env.hgeie, RISCVCPU),
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VMSTATE_UINTTL(env.hgeip, RISCVCPU),
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VMSTATE_UINT64(env.hvien, RISCVCPU),
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VMSTATE_UINT64(env.hvip, RISCVCPU),
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VMSTATE_UINT64(env.htimedelta, RISCVCPU),
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VMSTATE_UINT64(env.vstimecmp, RISCVCPU),
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VMSTATE_UINTTL(env.hvictl, RISCVCPU),
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VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
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VMSTATE_UINT64(env.vsstatus, RISCVCPU),
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VMSTATE_UINTTL(env.vstvec, RISCVCPU),
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VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
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VMSTATE_UINTTL(env.vsepc, RISCVCPU),
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VMSTATE_UINTTL(env.vscause, RISCVCPU),
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VMSTATE_UINTTL(env.vstval, RISCVCPU),
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VMSTATE_UINTTL(env.vsatp, RISCVCPU),
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VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
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VMSTATE_UINT64(env.vsie, RISCVCPU),
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VMSTATE_UINTTL(env.mtval2, RISCVCPU),
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VMSTATE_UINTTL(env.mtinst, RISCVCPU),
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VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
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VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
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VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
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VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
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VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
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VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
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VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool vector_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVV);
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}
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static const VMStateDescription vmstate_vector = {
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.name = "cpu/vector",
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.version_id = 2,
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.minimum_version_id = 2,
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.needed = vector_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
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VMSTATE_UINTTL(env.vxrm, RISCVCPU),
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VMSTATE_UINTTL(env.vxsat, RISCVCPU),
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VMSTATE_UINTTL(env.vl, RISCVCPU),
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VMSTATE_UINTTL(env.vstart, RISCVCPU),
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VMSTATE_UINTTL(env.vtype, RISCVCPU),
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VMSTATE_BOOL(env.vill, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool pointermasking_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVJ);
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}
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static const VMStateDescription vmstate_pointermasking = {
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.name = "cpu/pointer_masking",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pointermasking_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.mmte, RISCVCPU),
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VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
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VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
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VMSTATE_UINTTL(env.spmmask, RISCVCPU),
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VMSTATE_UINTTL(env.spmbase, RISCVCPU),
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VMSTATE_UINTTL(env.upmmask, RISCVCPU),
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VMSTATE_UINTTL(env.upmbase, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool rv128_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return env->misa_mxl_max == MXL_RV128;
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}
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static const VMStateDescription vmstate_rv128 = {
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.name = "cpu/rv128",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = rv128_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
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VMSTATE_UINT64(env.mscratchh, RISCVCPU),
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VMSTATE_UINT64(env.sscratchh, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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#ifdef CONFIG_KVM
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static bool kvmtimer_needed(void *opaque)
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{
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return kvm_enabled();
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}
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static int cpu_kvmtimer_post_load(void *opaque, int version_id)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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env->kvm_timer_dirty = true;
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return 0;
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}
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static const VMStateDescription vmstate_kvmtimer = {
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.name = "cpu/kvmtimer",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = kvmtimer_needed,
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.post_load = cpu_kvmtimer_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
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VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
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VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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#endif
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static bool debug_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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return cpu->cfg.debug;
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}
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static int debug_post_load(void *opaque, int version_id)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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if (icount_enabled()) {
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env->itrigger_enabled = riscv_itrigger_enabled(env);
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}
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return 0;
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}
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static const VMStateDescription vmstate_debug = {
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.name = "cpu/debug",
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.version_id = 2,
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.minimum_version_id = 2,
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.needed = debug_needed,
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.post_load = debug_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
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VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
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VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
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VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
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VMSTATE_END_OF_LIST()
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}
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};
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static int riscv_cpu_post_load(void *opaque, int version_id)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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env->xl = cpu_recompute_xl(env);
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riscv_cpu_update_mask(env);
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return 0;
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}
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static bool smstateen_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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return cpu->cfg.ext_smstateen;
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}
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static const VMStateDescription vmstate_smstateen = {
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.name = "cpu/smtateen",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = smstateen_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
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VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
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VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool envcfg_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
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}
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static const VMStateDescription vmstate_envcfg = {
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.name = "cpu/envcfg",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = envcfg_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.menvcfg, RISCVCPU),
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VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
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VMSTATE_UINT64(env.henvcfg, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool pmu_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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return cpu->cfg.pmu_num;
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}
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static const VMStateDescription vmstate_pmu_ctr_state = {
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.name = "cpu/pmu",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pmu_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
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VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
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VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
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VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
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VMSTATE_BOOL(started, PMUCTRState),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool jvt_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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return cpu->cfg.ext_zcmt;
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}
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static const VMStateDescription vmstate_jvt = {
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.name = "cpu/jvt",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = jvt_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.jvt, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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const VMStateDescription vmstate_riscv_cpu = {
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.name = "cpu",
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.version_id = 9,
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.minimum_version_id = 9,
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.post_load = riscv_cpu_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
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VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
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VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
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VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
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VMSTATE_UINTTL(env.pc, RISCVCPU),
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VMSTATE_UINTTL(env.load_res, RISCVCPU),
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VMSTATE_UINTTL(env.load_val, RISCVCPU),
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VMSTATE_UINTTL(env.frm, RISCVCPU),
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VMSTATE_UINTTL(env.badaddr, RISCVCPU),
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VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
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VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
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VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
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VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
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VMSTATE_UINT32(env.misa_ext, RISCVCPU),
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VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
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VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
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VMSTATE_UINTTL(env.priv, RISCVCPU),
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VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
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VMSTATE_UINT64(env.resetvec, RISCVCPU),
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VMSTATE_UINTTL(env.mhartid, RISCVCPU),
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VMSTATE_UINT64(env.mstatus, RISCVCPU),
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VMSTATE_UINT64(env.mip, RISCVCPU),
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VMSTATE_UINT64(env.miclaim, RISCVCPU),
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VMSTATE_UINT64(env.mie, RISCVCPU),
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VMSTATE_UINT64(env.mvien, RISCVCPU),
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VMSTATE_UINT64(env.mvip, RISCVCPU),
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VMSTATE_UINT64(env.sie, RISCVCPU),
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VMSTATE_UINT64(env.mideleg, RISCVCPU),
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VMSTATE_UINTTL(env.satp, RISCVCPU),
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VMSTATE_UINTTL(env.stval, RISCVCPU),
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VMSTATE_UINTTL(env.medeleg, RISCVCPU),
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VMSTATE_UINTTL(env.stvec, RISCVCPU),
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VMSTATE_UINTTL(env.sepc, RISCVCPU),
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VMSTATE_UINTTL(env.scause, RISCVCPU),
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VMSTATE_UINTTL(env.mtvec, RISCVCPU),
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VMSTATE_UINTTL(env.mepc, RISCVCPU),
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VMSTATE_UINTTL(env.mcause, RISCVCPU),
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VMSTATE_UINTTL(env.mtval, RISCVCPU),
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VMSTATE_UINTTL(env.miselect, RISCVCPU),
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VMSTATE_UINTTL(env.siselect, RISCVCPU),
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VMSTATE_UINTTL(env.scounteren, RISCVCPU),
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VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
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VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
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VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
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vmstate_pmu_ctr_state, PMUCTRState),
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VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
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VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
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VMSTATE_UINTTL(env.sscratch, RISCVCPU),
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VMSTATE_UINTTL(env.mscratch, RISCVCPU),
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VMSTATE_UINT64(env.stimecmp, RISCVCPU),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_pmp,
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&vmstate_hyper,
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&vmstate_vector,
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&vmstate_pointermasking,
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&vmstate_rv128,
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#ifdef CONFIG_KVM
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&vmstate_kvmtimer,
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#endif
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&vmstate_envcfg,
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&vmstate_debug,
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&vmstate_smstateen,
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&vmstate_jvt,
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NULL
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}
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};
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