4051e12c5d
The CPSR has a new-in-v8 execution state bit (IL), and also some state which has effects in AArch32 but appears only in the SPSR format (SS) but is RES0 in the CPSR. Add the IL bit to CPSR_EXEC, and enforce that guest direct reads and writes to CPSR can't read or write the RES0 bits, so the guest can't get at the SS bit which we store in uncached_cpsr. This includes not permitting exception returns to copy reserved bits from an SPSR into CPSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
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| .. | ||
| arm_ldst.h | ||
| arm-semi.c | ||
| cpu64.c | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| crypto_helper.c | ||
| gdbstub64.c | ||
| gdbstub.c | ||
| helper-a64.c | ||
| helper-a64.h | ||
| helper.c | ||
| helper.h | ||
| internals.h | ||
| iwmmxt_helper.c | ||
| kvm32.c | ||
| kvm64.c | ||
| kvm_arm.h | ||
| kvm-consts.h | ||
| kvm-stub.c | ||
| kvm.c | ||
| machine.c | ||
| Makefile.objs | ||
| neon_helper.c | ||
| op_addsub.h | ||
| op_helper.c | ||
| translate-a64.c | ||
| translate.c | ||
| translate.h | ||