Nathaniel Graff 40061ac0bc sifive_uart: Implement interrupt pending register ... The watermark bits are set in the interrupt pending register according to the configuration of txcnt and rxcnt in the txctrl and rxctrl registers. Since the UART TX does not implement a FIFO, the txwm bit is set as long as the TX watermark level is greater than zero. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-12-20 12:08:43 -08:00
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Makefile.objs
riscv_hart.c
riscv_htif.c
sifive_clint.c
sifive_e.c	RISC-V: Enable second UART on sifive_e and sifive_u	2018-12-20 12:08:43 -08:00
sifive_plic.c
sifive_prci.c
sifive_test.c
sifive_u.c	RISC-V: Enable second UART on sifive_e and sifive_u	2018-12-20 12:08:43 -08:00
sifive_uart.c	sifive_uart: Implement interrupt pending register	2018-12-20 12:08:43 -08:00
spike.c
virt.c