320 lines
9.6 KiB
C
320 lines
9.6 KiB
C
/*
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* QEMU PowerPC E500 embedded processors pci controller emulation
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* This file is derived from hw/ppc4xx_pci.c,
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* the copyright for that material belongs to the original owners.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "hw.h"
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#include "ppce500.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "bswap.h"
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#ifdef DEBUG_PCI
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#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
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#else
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#define pci_debug(fmt, ...)
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#endif
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#define PCIE500_CFGADDR 0x0
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#define PCIE500_CFGDATA 0x4
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#define PCIE500_REG_BASE 0xC00
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#define PCIE500_REG_SIZE (0x1000 - PCIE500_REG_BASE)
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#define PPCE500_PCI_CONFIG_ADDR 0x0
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#define PPCE500_PCI_CONFIG_DATA 0x4
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#define PPCE500_PCI_INTACK 0x8
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#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
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#define PCI_POTAR 0x0
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#define PCI_POTEAR 0x4
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#define PCI_POWBAR 0x8
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#define PCI_POWAR 0x10
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#define PCI_PITAR 0x0
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#define PCI_PIWBAR 0x8
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#define PCI_PIWBEAR 0xC
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#define PCI_PIWAR 0x10
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#define PPCE500_PCI_NR_POBS 5
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#define PPCE500_PCI_NR_PIBS 3
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struct pci_outbound {
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uint32_t potar;
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uint32_t potear;
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uint32_t powbar;
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uint32_t powar;
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};
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struct pci_inbound {
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uint32_t pitar;
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uint32_t piwbar;
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uint32_t piwbear;
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uint32_t piwar;
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};
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struct PPCE500PCIState {
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struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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uint32_t gasket_time;
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PCIHostState pci_state;
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PCIDevice *pci_dev;
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};
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typedef struct PPCE500PCIState PPCE500PCIState;
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static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
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{
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PPCE500PCIState *pci = opaque;
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unsigned long win;
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uint32_t value = 0;
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win = addr & 0xfe0;
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switch (win) {
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case PPCE500_PCI_OW1:
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case PPCE500_PCI_OW2:
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case PPCE500_PCI_OW3:
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case PPCE500_PCI_OW4:
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switch (addr & 0xC) {
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case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
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case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
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case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
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case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
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default: break;
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}
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break;
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case PPCE500_PCI_IW3:
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case PPCE500_PCI_IW2:
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case PPCE500_PCI_IW1:
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switch (addr & 0xC) {
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case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
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case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
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case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
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case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
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default: break;
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};
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break;
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case PPCE500_PCI_GASKET_TIMR:
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value = pci->gasket_time;
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break;
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default:
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break;
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}
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pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
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win, addr, value);
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return value;
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}
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static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
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&pci_reg_read4,
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&pci_reg_read4,
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&pci_reg_read4,
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};
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static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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PPCE500PCIState *pci = opaque;
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unsigned long win;
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win = addr & 0xfe0;
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pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
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__func__, value, win, addr);
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switch (win) {
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case PPCE500_PCI_OW1:
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case PPCE500_PCI_OW2:
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case PPCE500_PCI_OW3:
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case PPCE500_PCI_OW4:
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switch (addr & 0xC) {
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case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
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case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
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case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
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case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
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default: break;
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};
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break;
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case PPCE500_PCI_IW3:
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case PPCE500_PCI_IW2:
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case PPCE500_PCI_IW1:
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switch (addr & 0xC) {
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case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
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case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
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case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
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case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
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default: break;
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};
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break;
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case PPCE500_PCI_GASKET_TIMR:
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pci->gasket_time = value;
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break;
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default:
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break;
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};
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}
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static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
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&pci_reg_write4,
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&pci_reg_write4,
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&pci_reg_write4,
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};
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static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int devno = pci_dev->devfn >> 3, ret = 0;
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switch (devno) {
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/* Two PCI slot */
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case 0x11:
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case 0x12:
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ret = (irq_num + devno - 0x10) % 4;
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break;
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default:
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printf("Error:%s:unknown dev number\n", __func__);
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}
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pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
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pci_dev->devfn, irq_num, ret, devno);
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return ret;
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}
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static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
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qemu_set_irq(pic[irq_num], level);
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}
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static const VMStateDescription vmstate_pci_outbound = {
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.name = "pci_outbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(potar, struct pci_outbound),
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VMSTATE_UINT32(potear, struct pci_outbound),
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VMSTATE_UINT32(powbar, struct pci_outbound),
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VMSTATE_UINT32(powar, struct pci_outbound),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pci_inbound = {
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.name = "pci_inbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(pitar, struct pci_inbound),
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VMSTATE_UINT32(piwbar, struct pci_inbound),
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VMSTATE_UINT32(piwbear, struct pci_inbound),
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VMSTATE_UINT32(piwar, struct pci_inbound),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_ppce500_pci = {
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.name = "ppce500_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPCE500PCIState),
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VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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vmstate_pci_outbound, struct pci_outbound),
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VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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vmstate_pci_outbound, struct pci_inbound),
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VMSTATE_UINT32(gasket_time, PPCE500PCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
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{
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PPCE500PCIState *controller;
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PCIDevice *d;
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int index;
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static int ppce500_pci_id;
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controller = qemu_mallocz(sizeof(PPCE500PCIState));
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controller->pci_state.bus = pci_register_bus(NULL, "pci",
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mpc85xx_pci_set_irq,
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mpc85xx_pci_map_irq,
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pci_irqs, PCI_DEVFN(0x11, 0),
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4);
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d = pci_register_device(controller->pci_state.bus,
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"host bridge", sizeof(PCIDevice),
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0, NULL, NULL);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
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pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);
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controller->pci_dev = d;
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/* CFGADDR */
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index = pci_host_conf_register_mmio(&controller->pci_state,
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DEVICE_BIG_ENDIAN);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
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/* CFGDATA */
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index = pci_host_data_register_mmio(&controller->pci_state,
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DEVICE_BIG_ENDIAN);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
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index = cpu_register_io_memory(e500_pci_reg_read,
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e500_pci_reg_write, controller,
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DEVICE_NATIVE_ENDIAN);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_REG_BASE,
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PCIE500_REG_SIZE, index);
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/* XXX load/save code not tested. */
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vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci,
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controller);
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return controller->pci_state.bus;
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free:
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printf("%s error\n", __func__);
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qemu_free(controller);
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return NULL;
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}
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