828d651c58
A device shouldn't access its parent object which is QOM internal. Instead it should use type cast for this purporse. This patch fixes this issue for all NPCM7XX Devices. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210108190945.949196-7-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
573 lines
18 KiB
C
573 lines
18 KiB
C
/*
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* Nuvoton NPCM7xx Flash Interface Unit (FIU)
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/ssi/npcm7xx_fiu.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "trace.h"
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/* Up to 128 MiB of flash may be accessed directly as memory. */
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#define NPCM7XX_FIU_FLASH_WINDOW_SIZE (128 * MiB)
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/* Each module has 4 KiB of register space. Only a fraction of it is used. */
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#define NPCM7XX_FIU_CTRL_REGS_SIZE (4 * KiB)
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/* 32-bit FIU register indices. */
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enum NPCM7xxFIURegister {
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NPCM7XX_FIU_DRD_CFG,
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NPCM7XX_FIU_DWR_CFG,
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NPCM7XX_FIU_UMA_CFG,
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NPCM7XX_FIU_UMA_CTS,
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NPCM7XX_FIU_UMA_CMD,
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NPCM7XX_FIU_UMA_ADDR,
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NPCM7XX_FIU_PRT_CFG,
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NPCM7XX_FIU_UMA_DW0 = 0x0020 / sizeof(uint32_t),
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NPCM7XX_FIU_UMA_DW1,
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NPCM7XX_FIU_UMA_DW2,
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NPCM7XX_FIU_UMA_DW3,
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NPCM7XX_FIU_UMA_DR0,
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NPCM7XX_FIU_UMA_DR1,
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NPCM7XX_FIU_UMA_DR2,
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NPCM7XX_FIU_UMA_DR3,
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NPCM7XX_FIU_PRT_CMD0,
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NPCM7XX_FIU_PRT_CMD1,
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NPCM7XX_FIU_PRT_CMD2,
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NPCM7XX_FIU_PRT_CMD3,
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NPCM7XX_FIU_PRT_CMD4,
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NPCM7XX_FIU_PRT_CMD5,
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NPCM7XX_FIU_PRT_CMD6,
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NPCM7XX_FIU_PRT_CMD7,
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NPCM7XX_FIU_PRT_CMD8,
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NPCM7XX_FIU_PRT_CMD9,
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NPCM7XX_FIU_CFG = 0x78 / sizeof(uint32_t),
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NPCM7XX_FIU_REGS_END,
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};
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/* FIU_{DRD,DWR,UMA,PTR}_CFG cannot be written when this bit is set. */
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#define NPCM7XX_FIU_CFG_LCK BIT(31)
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/* Direct Read configuration register fields. */
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#define FIU_DRD_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
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#define FIU_ADDSIZ_3BYTES 0
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#define FIU_ADDSIZ_4BYTES 1
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#define FIU_DRD_CFG_DBW(rv) extract32(rv, 12, 2)
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#define FIU_DRD_CFG_ACCTYPE(rv) extract32(rv, 8, 2)
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#define FIU_DRD_CFG_RDCMD(rv) extract32(rv, 0, 8)
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/* Direct Write configuration register fields. */
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#define FIU_DWR_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
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#define FIU_DWR_CFG_WRCMD(rv) extract32(rv, 0, 8)
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/* User-Mode Access register fields. */
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/* Command Mode Lock and the bits protected by it. */
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#define FIU_UMA_CFG_CMMLCK BIT(30)
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#define FIU_UMA_CFG_CMMLCK_MASK 0x00000403
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#define FIU_UMA_CFG_RDATSIZ(rv) extract32(rv, 24, 5)
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#define FIU_UMA_CFG_DBSIZ(rv) extract32(rv, 21, 3)
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#define FIU_UMA_CFG_WDATSIZ(rv) extract32(rv, 16, 5)
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#define FIU_UMA_CFG_ADDSIZ(rv) extract32(rv, 11, 3)
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#define FIU_UMA_CFG_CMDSIZ(rv) extract32(rv, 10, 1)
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#define FIU_UMA_CFG_DBPCK(rv) extract32(rv, 6, 2)
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#define FIU_UMA_CTS_RDYIE BIT(25)
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#define FIU_UMA_CTS_RDYST BIT(24)
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#define FIU_UMA_CTS_SW_CS BIT(16)
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#define FIU_UMA_CTS_DEV_NUM(rv) extract32(rv, 8, 2)
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#define FIU_UMA_CTS_EXEC_DONE BIT(0)
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/*
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* Returns the index of flash in the fiu->flash array. This corresponds to the
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* chip select ID of the flash.
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*/
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static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu,
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NPCM7xxFIUFlash *flash)
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{
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int index = flash - fiu->flash;
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g_assert(index >= 0 && index < fiu->cs_count);
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return index;
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}
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/* Assert the chip select specified in the UMA Control/Status Register. */
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static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id)
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{
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trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
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if (cs_id < s->cs_count) {
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qemu_irq_lower(s->cs_lines[cs_id]);
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s->active_cs = cs_id;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: UMA to CS%d; this module has only %d chip selects",
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DEVICE(s)->canonical_path, cs_id, s->cs_count);
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s->active_cs = -1;
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}
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}
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/* Deassert the currently active chip select. */
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static void npcm7xx_fiu_deselect(NPCM7xxFIUState *s)
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{
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if (s->active_cs < 0) {
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return;
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}
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trace_npcm7xx_fiu_deselect(DEVICE(s)->canonical_path, s->active_cs);
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qemu_irq_raise(s->cs_lines[s->active_cs]);
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s->active_cs = -1;
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}
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/* Direct flash memory read handler. */
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static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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NPCM7xxFIUFlash *f = opaque;
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NPCM7xxFIUState *fiu = f->fiu;
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uint64_t value = 0;
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uint32_t drd_cfg;
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int dummy_cycles;
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int i;
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if (fiu->active_cs != -1) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: direct flash read with CS%d already active",
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DEVICE(fiu)->canonical_path, fiu->active_cs);
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}
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npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));
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drd_cfg = fiu->regs[NPCM7XX_FIU_DRD_CFG];
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ssi_transfer(fiu->spi, FIU_DRD_CFG_RDCMD(drd_cfg));
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switch (FIU_DRD_CFG_ADDSIZ(drd_cfg)) {
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case FIU_ADDSIZ_4BYTES:
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ssi_transfer(fiu->spi, extract32(addr, 24, 8));
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/* fall through */
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case FIU_ADDSIZ_3BYTES:
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ssi_transfer(fiu->spi, extract32(addr, 16, 8));
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ssi_transfer(fiu->spi, extract32(addr, 8, 8));
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ssi_transfer(fiu->spi, extract32(addr, 0, 8));
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
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DEVICE(fiu)->canonical_path, FIU_DRD_CFG_ADDSIZ(drd_cfg));
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break;
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}
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/* Flash chip model expects one transfer per dummy bit, not byte */
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dummy_cycles =
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(FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
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for (i = 0; i < dummy_cycles; i++) {
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ssi_transfer(fiu->spi, 0);
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}
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for (i = 0; i < size; i++) {
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value = deposit64(value, 8 * i, 8, ssi_transfer(fiu->spi, 0));
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}
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trace_npcm7xx_fiu_flash_read(DEVICE(fiu)->canonical_path, fiu->active_cs,
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addr, size, value);
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npcm7xx_fiu_deselect(fiu);
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return value;
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}
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/* Direct flash memory write handler. */
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static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
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unsigned int size)
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{
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NPCM7xxFIUFlash *f = opaque;
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NPCM7xxFIUState *fiu = f->fiu;
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uint32_t dwr_cfg;
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unsigned cs_id;
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int i;
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if (fiu->active_cs != -1) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: direct flash write with CS%d already active",
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DEVICE(fiu)->canonical_path, fiu->active_cs);
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}
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cs_id = npcm7xx_fiu_cs_index(fiu, f);
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trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
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size, v);
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npcm7xx_fiu_select(fiu, cs_id);
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dwr_cfg = fiu->regs[NPCM7XX_FIU_DWR_CFG];
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ssi_transfer(fiu->spi, FIU_DWR_CFG_WRCMD(dwr_cfg));
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switch (FIU_DWR_CFG_ADDSIZ(dwr_cfg)) {
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case FIU_ADDSIZ_4BYTES:
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ssi_transfer(fiu->spi, extract32(addr, 24, 8));
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/* fall through */
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case FIU_ADDSIZ_3BYTES:
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ssi_transfer(fiu->spi, extract32(addr, 16, 8));
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ssi_transfer(fiu->spi, extract32(addr, 8, 8));
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ssi_transfer(fiu->spi, extract32(addr, 0, 8));
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
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DEVICE(fiu)->canonical_path, FIU_DWR_CFG_ADDSIZ(dwr_cfg));
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break;
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}
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for (i = 0; i < size; i++) {
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ssi_transfer(fiu->spi, extract64(v, i * 8, 8));
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}
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npcm7xx_fiu_deselect(fiu);
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}
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static const MemoryRegionOps npcm7xx_fiu_flash_ops = {
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.read = npcm7xx_fiu_flash_read,
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.write = npcm7xx_fiu_flash_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = true,
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},
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};
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/* Control register read handler. */
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static uint64_t npcm7xx_fiu_ctrl_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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hwaddr reg = addr / sizeof(uint32_t);
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NPCM7xxFIUState *s = opaque;
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uint32_t value;
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if (reg < NPCM7XX_FIU_NR_REGS) {
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value = s->regs[reg];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: read from invalid offset 0x%" PRIx64 "\n",
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DEVICE(s)->canonical_path, addr);
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value = 0;
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}
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trace_npcm7xx_fiu_ctrl_read(DEVICE(s)->canonical_path, addr, value);
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return value;
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}
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/* Send the specified number of address bytes from the UMA address register. */
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static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr)
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{
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switch (addsiz) {
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case 4:
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ssi_transfer(spi, extract32(addr, 24, 8));
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/* fall through */
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case 3:
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ssi_transfer(spi, extract32(addr, 16, 8));
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/* fall through */
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case 2:
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ssi_transfer(spi, extract32(addr, 8, 8));
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/* fall through */
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case 1:
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ssi_transfer(spi, extract32(addr, 0, 8));
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/* fall through */
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case 0:
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break;
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}
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}
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/* Send the number of dummy bits specified in the UMA config register. */
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static void send_dummy_bits(SSIBus *spi, uint32_t uma_cfg, uint32_t uma_cmd)
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{
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unsigned int bits_per_clock = 1U << FIU_UMA_CFG_DBPCK(uma_cfg);
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unsigned int i;
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for (i = 0; i < FIU_UMA_CFG_DBSIZ(uma_cfg); i++) {
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/* Use bytes 0 and 1 first, then keep repeating byte 2 */
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unsigned int field = (i < 2) ? ((i + 1) * 8) : 24;
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unsigned int j;
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for (j = 0; j < 8; j += bits_per_clock) {
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ssi_transfer(spi, extract32(uma_cmd, field + j, bits_per_clock));
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}
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}
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}
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/* Perform a User-Mode Access transaction. */
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static void npcm7xx_fiu_uma_transaction(NPCM7xxFIUState *s)
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{
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uint32_t uma_cts = s->regs[NPCM7XX_FIU_UMA_CTS];
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uint32_t uma_cfg;
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unsigned int i;
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/* SW_CS means the CS is already forced low, so don't touch it. */
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if (uma_cts & FIU_UMA_CTS_SW_CS) {
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int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
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npcm7xx_fiu_select(s, cs_id);
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}
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/* Send command, if present. */
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uma_cfg = s->regs[NPCM7XX_FIU_UMA_CFG];
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if (FIU_UMA_CFG_CMDSIZ(uma_cfg) > 0) {
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ssi_transfer(s->spi, extract32(s->regs[NPCM7XX_FIU_UMA_CMD], 0, 8));
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}
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/* Send address, if present. */
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send_address(s->spi, FIU_UMA_CFG_ADDSIZ(uma_cfg),
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s->regs[NPCM7XX_FIU_UMA_ADDR]);
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/* Write data, if present. */
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for (i = 0; i < FIU_UMA_CFG_WDATSIZ(uma_cfg); i++) {
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unsigned int reg =
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(i < 16) ? (NPCM7XX_FIU_UMA_DW0 + i / 4) : NPCM7XX_FIU_UMA_DW3;
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unsigned int field = (i % 4) * 8;
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ssi_transfer(s->spi, extract32(s->regs[reg], field, 8));
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}
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/* Send dummy bits, if present. */
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send_dummy_bits(s->spi, uma_cfg, s->regs[NPCM7XX_FIU_UMA_CMD]);
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/* Read data, if present. */
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for (i = 0; i < FIU_UMA_CFG_RDATSIZ(uma_cfg); i++) {
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unsigned int reg = NPCM7XX_FIU_UMA_DR0 + i / 4;
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unsigned int field = (i % 4) * 8;
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uint8_t c;
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c = ssi_transfer(s->spi, 0);
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if (reg <= NPCM7XX_FIU_UMA_DR3) {
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s->regs[reg] = deposit32(s->regs[reg], field, 8, c);
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}
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}
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/* Again, don't touch CS if the user is forcing it low. */
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if (uma_cts & FIU_UMA_CTS_SW_CS) {
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npcm7xx_fiu_deselect(s);
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}
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/* RDYST means a command has completed since it was cleared. */
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s->regs[NPCM7XX_FIU_UMA_CTS] |= FIU_UMA_CTS_RDYST;
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/* EXEC_DONE means Execute Command / Not Done, so clear it here. */
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s->regs[NPCM7XX_FIU_UMA_CTS] &= ~FIU_UMA_CTS_EXEC_DONE;
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}
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/* Control register write handler. */
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static void npcm7xx_fiu_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
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unsigned int size)
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{
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hwaddr reg = addr / sizeof(uint32_t);
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NPCM7xxFIUState *s = opaque;
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uint32_t value = v;
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trace_npcm7xx_fiu_ctrl_write(DEVICE(s)->canonical_path, addr, value);
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switch (reg) {
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case NPCM7XX_FIU_UMA_CFG:
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if (s->regs[reg] & FIU_UMA_CFG_CMMLCK) {
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value &= ~FIU_UMA_CFG_CMMLCK_MASK;
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value |= (s->regs[reg] & FIU_UMA_CFG_CMMLCK_MASK);
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}
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/* fall through */
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case NPCM7XX_FIU_DRD_CFG:
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case NPCM7XX_FIU_DWR_CFG:
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if (s->regs[reg] & NPCM7XX_FIU_CFG_LCK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to locked register @ 0x%" PRIx64 "\n",
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DEVICE(s)->canonical_path, addr);
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return;
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}
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s->regs[reg] = value;
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break;
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case NPCM7XX_FIU_UMA_CTS:
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if (value & FIU_UMA_CTS_RDYST) {
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value &= ~FIU_UMA_CTS_RDYST;
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} else {
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value |= s->regs[reg] & FIU_UMA_CTS_RDYST;
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}
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if ((s->regs[reg] ^ value) & FIU_UMA_CTS_SW_CS) {
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if (value & FIU_UMA_CTS_SW_CS) {
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/*
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* Don't drop CS if there's a transfer in progress, or we're
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* about to start one.
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*/
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if (!((value | s->regs[reg]) & FIU_UMA_CTS_EXEC_DONE)) {
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npcm7xx_fiu_deselect(s);
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}
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} else {
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int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
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npcm7xx_fiu_select(s, cs_id);
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}
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}
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s->regs[reg] = value | (s->regs[reg] & FIU_UMA_CTS_EXEC_DONE);
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if (value & FIU_UMA_CTS_EXEC_DONE) {
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npcm7xx_fiu_uma_transaction(s);
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}
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break;
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case NPCM7XX_FIU_UMA_DR0 ... NPCM7XX_FIU_UMA_DR3:
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qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: write to read-only register @ 0x%" PRIx64 "\n",
|
|
DEVICE(s)->canonical_path, addr);
|
|
return;
|
|
|
|
case NPCM7XX_FIU_PRT_CFG:
|
|
case NPCM7XX_FIU_PRT_CMD0 ... NPCM7XX_FIU_PRT_CMD9:
|
|
qemu_log_mask(LOG_UNIMP, "%s: PRT is not implemented\n", __func__);
|
|
break;
|
|
|
|
case NPCM7XX_FIU_UMA_CMD:
|
|
case NPCM7XX_FIU_UMA_ADDR:
|
|
case NPCM7XX_FIU_UMA_DW0 ... NPCM7XX_FIU_UMA_DW3:
|
|
case NPCM7XX_FIU_CFG:
|
|
s->regs[reg] = value;
|
|
break;
|
|
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: write to invalid offset 0x%" PRIx64 "\n",
|
|
DEVICE(s)->canonical_path, addr);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps npcm7xx_fiu_ctrl_ops = {
|
|
.read = npcm7xx_fiu_ctrl_read,
|
|
.write = npcm7xx_fiu_ctrl_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
.unaligned = false,
|
|
},
|
|
};
|
|
|
|
static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type)
|
|
{
|
|
NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
|
|
|
|
trace_npcm7xx_fiu_enter_reset(DEVICE(obj)->canonical_path, type);
|
|
|
|
memset(s->regs, 0, sizeof(s->regs));
|
|
|
|
s->regs[NPCM7XX_FIU_DRD_CFG] = 0x0300100b;
|
|
s->regs[NPCM7XX_FIU_DWR_CFG] = 0x03000002;
|
|
s->regs[NPCM7XX_FIU_UMA_CFG] = 0x00000400;
|
|
s->regs[NPCM7XX_FIU_UMA_CTS] = 0x00010000;
|
|
s->regs[NPCM7XX_FIU_UMA_CMD] = 0x0000000b;
|
|
s->regs[NPCM7XX_FIU_PRT_CFG] = 0x00000400;
|
|
s->regs[NPCM7XX_FIU_CFG] = 0x0000000b;
|
|
}
|
|
|
|
static void npcm7xx_fiu_hold_reset(Object *obj)
|
|
{
|
|
NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
|
|
int i;
|
|
|
|
trace_npcm7xx_fiu_hold_reset(DEVICE(obj)->canonical_path);
|
|
|
|
for (i = 0; i < s->cs_count; i++) {
|
|
qemu_irq_raise(s->cs_lines[i]);
|
|
}
|
|
}
|
|
|
|
static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
int i;
|
|
|
|
if (s->cs_count <= 0) {
|
|
error_setg(errp, "%s: %d chip selects specified, need at least one",
|
|
dev->canonical_path, s->cs_count);
|
|
return;
|
|
}
|
|
|
|
s->spi = ssi_create_bus(dev, "spi");
|
|
s->cs_lines = g_new0(qemu_irq, s->cs_count);
|
|
qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", s->cs_count);
|
|
s->flash = g_new0(NPCM7xxFIUFlash, s->cs_count);
|
|
|
|
/*
|
|
* Register the control registers region first. It may be followed by one
|
|
* or more direct flash access regions.
|
|
*/
|
|
memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_fiu_ctrl_ops, s, "ctrl",
|
|
NPCM7XX_FIU_CTRL_REGS_SIZE);
|
|
sysbus_init_mmio(sbd, &s->mmio);
|
|
|
|
for (i = 0; i < s->cs_count; i++) {
|
|
NPCM7xxFIUFlash *flash = &s->flash[i];
|
|
flash->fiu = s;
|
|
memory_region_init_io(&flash->direct_access, OBJECT(s),
|
|
&npcm7xx_fiu_flash_ops, &s->flash[i], "flash",
|
|
NPCM7XX_FIU_FLASH_WINDOW_SIZE);
|
|
sysbus_init_mmio(sbd, &flash->direct_access);
|
|
}
|
|
}
|
|
|
|
static const VMStateDescription vmstate_npcm7xx_fiu = {
|
|
.name = "npcm7xx-fiu",
|
|
.version_id = 0,
|
|
.minimum_version_id = 0,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32(active_cs, NPCM7xxFIUState),
|
|
VMSTATE_UINT32_ARRAY(regs, NPCM7xxFIUState, NPCM7XX_FIU_NR_REGS),
|
|
VMSTATE_END_OF_LIST(),
|
|
},
|
|
};
|
|
|
|
static Property npcm7xx_fiu_properties[] = {
|
|
DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void npcm7xx_fiu_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
QEMU_BUILD_BUG_ON(NPCM7XX_FIU_REGS_END > NPCM7XX_FIU_NR_REGS);
|
|
|
|
dc->desc = "NPCM7xx Flash Interface Unit";
|
|
dc->realize = npcm7xx_fiu_realize;
|
|
dc->vmsd = &vmstate_npcm7xx_fiu;
|
|
rc->phases.enter = npcm7xx_fiu_enter_reset;
|
|
rc->phases.hold = npcm7xx_fiu_hold_reset;
|
|
device_class_set_props(dc, npcm7xx_fiu_properties);
|
|
}
|
|
|
|
static const TypeInfo npcm7xx_fiu_types[] = {
|
|
{
|
|
.name = TYPE_NPCM7XX_FIU,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(NPCM7xxFIUState),
|
|
.class_init = npcm7xx_fiu_class_init,
|
|
},
|
|
};
|
|
DEFINE_TYPES(npcm7xx_fiu_types);
|