Bin Meng e79d27cb32 hw/riscv: sifive_e: Correct debug block size ... Currently the debug region size is set to 0x100, but according to FE310-G000 and FE310-G002 manuals: FE310-G000: 0x100 - 0xFFF FE310-G002: 0x0 - 0xFFF Change the size to 0x1000 that applies to both. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-22 09:39:46 -07:00
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boot.c
Kconfig
Makefile.objs
opentitan.c
riscv_hart.c
riscv_htif.c
sifive_clint.c
sifive_e_prci.c
sifive_e.c	hw/riscv: sifive_e: Correct debug block size	2020-07-22 09:39:46 -07:00
sifive_gpio.c
sifive_plic.c
sifive_test.c
sifive_u_otp.c
sifive_u_prci.c
sifive_u.c	hw: Mark nd_table[] misuse in realize methods FIXME	2020-07-21 08:41:15 +02:00
sifive_uart.c
spike.c	hw/riscv: Modify MROM size to end at 0x10000	2020-07-13 17:25:37 -07:00
trace-events
virt.c	hw/riscv: Modify MROM size to end at 0x10000	2020-07-13 17:25:37 -07:00