Peter Maydell 4240fb6175 target/arm: Convert Extract instructions to decodetree ... Convert the EXTR instruction to decodetree (this is the only one in the 'Extract" class). This is the last of the dp-immediate insns in the legacy decoder, so we can now remove disas_data_proc_imm(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-13-peter.maydell@linaro.org		2023-05-18 11:28:39 +01:00
..
alpha	target/alpha: Use MO_ALIGN where required	2023-05-05 17:05:58 +01:00
arm	target/arm: Convert Extract instructions to decodetree	2023-05-18 11:28:39 +01:00
avr	target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*	2023-05-05 17:05:28 +01:00
cris	target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*	2023-05-05 17:05:28 +01:00
hexagon	target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*	2023-05-05 17:05:28 +01:00
hppa	target/hppa: Use MO_ALIGN for system UNALIGN()	2023-05-05 17:05:58 +01:00
i386	target/i386: Add EPYC-Genoa model to support Zen 4 processor series	2023-05-08 16:35:30 +02:00
loongarch	target/loongarch: Do not include tcg-ldst.h	2023-05-11 09:53:41 +01:00
m68k	target/m68k: Fix gen_load_fp for OS_LONG	2023-05-11 09:49:25 +01:00
microblaze
mips	target/mips: Use MO_ALIGN instead of 0	2023-05-11 09:53:41 +01:00
nios2	target/nios2: Remove TARGET_ALIGNED_ONLY	2023-05-11 09:53:41 +01:00
openrisc	target/openrisc: Setup FPU for detecting tininess before rounding	2023-05-11 15:40:28 +01:00
ppc	tcg: ppc64: Fix mask generation for vextractdm	2023-05-05 12:34:22 -03:00
riscv	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
rx
s390x	target/s390x: Fix EXECUTE of relative branches	2023-05-16 09:14:18 +02:00
sh4	target/sh4: Use MO_ALIGN where required	2023-05-11 09:53:41 +01:00
sparc	target/sparc: Use cpu_ld*_code_mmu	2023-05-05 17:09:47 +01:00
tricore
xtensa	target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*	2023-05-05 17:05:29 +01:00
Kconfig
meson.build