586803455b
Fix audio on software that accesses DRAM above 64k via register
peek/poke and some cases when more than 16 voices are used.
Cc: qemu-stable@nongnu.org
Fixes: 135f5ae197 ("audio: GUSsample is int16_t")
Signed-off-by: Allan Peramaki <aperamak@pp1.inet.fi>
Tested-by: Volker Rümelin <vr_qemu@t-online.de>
Reviewed-by: Volker Rümelin <vr_qemu@t-online.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200618103623.6031-1-philmd@redhat.com
Message-Id: <20200615201757.16868-1-aperamak@pp1.inet.fi>
[PMD: Removed unrelated style changes]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
557 lines
23 KiB
C
557 lines
23 KiB
C
/*
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* GUSEMU32 - bus interface part
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*
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* Copyright (C) 2000-2007 Tibor "TS" Schütz
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* TODO: check mixer: see 7.20 of sdk for panning pos (applies to all gus models?)?
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*/
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#include "qemu/osdep.h"
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#include "gustate.h"
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#include "gusemu.h"
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#define GUSregb(position) (* (gusptr+(position)))
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#define GUSregw(position) (*(uint16_t *) (gusptr+(position)))
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#define GUSregd(position) (*(uint32_t *)(gusptr + (position)))
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/* size given in bytes */
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unsigned int gus_read(GUSEmuState * state, int port, int size)
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{
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int value_read = 0;
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uint8_t *gusptr;
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gusptr = state->gusdatapos;
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GUSregd(portaccesses)++;
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switch (port & 0xff0f)
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{
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/* MixerCtrlReg (read not supported on GUS classic) */
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/* case 0x200: return GUSregb(MixerCtrlReg2x0); */
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case 0x206: /* IRQstatReg / SB2x6IRQ */
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/* adlib/sb bits set in port handlers */
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/* timer/voice bits set in gus_irqgen() */
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/* dma bit set in gus_dma_transferdata */
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/* midi not implemented yet */
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return GUSregb(IRQStatReg2x6);
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/* case 0x308: */ /* AdLib388 */
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case 0x208:
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if (GUSregb(GUS45TimerCtrl) & 1)
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return GUSregb(TimerStatus2x8);
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return GUSregb(AdLibStatus2x8); /* AdLibStatus */
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case 0x309: /* AdLib389 */
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case 0x209:
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return GUSregb(AdLibData2x9); /* AdLibData */
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case 0x20A:
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return GUSregb(AdLibCommand2xA); /* AdLib2x8_2xA */
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#if 0
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case 0x20B: /* GUS hidden registers (read not supported on GUS classic) */
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switch (GUSregb(RegCtrl_2xF) & 0x07)
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{
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case 0: /* IRQ/DMA select */
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if (GUSregb(MixerCtrlReg2x0) & 0x40)
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return GUSregb(IRQ_2xB); /* control register select bit */
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else
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return GUSregb(DMA_2xB);
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/* case 1-5: */ /* general purpose emulation regs */
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/* return ... */ /* + status reset reg (write only) */
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case 6:
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return GUSregb(Jumper_2xB); /* Joystick/MIDI enable (JumperReg) */
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default:;
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}
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break;
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#endif
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case 0x20C: /* SB2xCd */
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value_read = GUSregb(SB2xCd);
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if (GUSregb(StatRead_2xF) & 0x20)
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GUSregb(SB2xCd) ^= 0x80; /* toggle MSB on read */
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return value_read;
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/* case 0x20D: */ /* SB2xD is write only -> 2xE writes to it*/
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case 0x20E:
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if (GUSregb(RegCtrl_2xF) & 0x80) /* 2xE read IRQ enabled? */
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{
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GUSregb(StatRead_2xF) |= 0x80;
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GUS_irqrequest(state, state->gusirq, 1);
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}
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return GUSregb(SB2xE); /* SB2xE */
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case 0x20F: /* StatRead_2xF */
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/*set/clear fixed bits */
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/*value_read = (GUSregb(StatRead_2xF) & 0xf9)|1; */ /*(LSB not set on GUS classic!)*/
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value_read = (GUSregb(StatRead_2xF) & 0xf9);
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if (GUSregb(MixerCtrlReg2x0) & 0x08)
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value_read |= 2; /* DMA/IRQ enabled flag */
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return value_read;
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/* case 0x300: */ /* MIDI (not implemented) */
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/* case 0x301: */ /* MIDI (not implemented) */
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case 0x302:
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return GUSregb(VoiceSelReg3x2); /* VoiceSelReg */
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case 0x303:
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return GUSregb(FunkSelReg3x3); /* FunkSelReg */
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case 0x304: /* DataRegLoByte3x4 + DataRegWord3x4 */
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case 0x305: /* DataRegHiByte3x5 */
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switch (GUSregb(FunkSelReg3x3))
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{
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/* common functions */
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case 0x41: /* DramDMAContrReg */
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value_read = GUSregb(GUS41DMACtrl); /* &0xfb */
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GUSregb(GUS41DMACtrl) &= 0xbb;
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if (state->gusdma >= 4)
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value_read |= 0x04;
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if (GUSregb(IRQStatReg2x6) & 0x80)
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{
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value_read |= 0x40;
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GUSregb(IRQStatReg2x6) &= 0x7f;
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq);
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}
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return (uint8_t) value_read;
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/* DramDMAmemPosReg */
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/* case 0x42: value_read=GUSregw(GUS42DMAStart); break;*/
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/* 43h+44h write only */
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case 0x45:
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return GUSregb(GUS45TimerCtrl); /* TimerCtrlReg */
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/* 46h+47h write only */
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/* 48h: samp freq - write only */
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case 0x49:
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return GUSregb(GUS49SampCtrl) & 0xbf; /* SampCtrlReg */
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/* case 4bh: */ /* joystick trim not supported */
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/* case 0x4c: return GUSregb(GUS4cReset); */ /* GUSreset: write only*/
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/* voice specific functions */
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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case 0x84:
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case 0x85:
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case 0x86:
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case 0x87:
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case 0x88:
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case 0x89:
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case 0x8a:
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case 0x8b:
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case 0x8c:
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case 0x8d:
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{
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int offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
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offset += ((int) GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Funktion*2 */
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value_read = GUSregw(offset);
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}
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break;
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/* voice unspecific functions */
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case 0x8e: /* NumVoice */
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return GUSregb(NumVoices);
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case 0x8f: /* irqstatreg */
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/* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */
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return GUSregb(SynVoiceIRQ8f);
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default:
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return 0xffff;
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}
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if (size == 1)
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{
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if ((port & 0xff0f) == 0x305)
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value_read = value_read >> 8;
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value_read &= 0xff;
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}
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return (uint16_t) value_read;
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/* case 0x306: */ /* Mixer/Version info */
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/* return 0xff; */ /* Pre 3.6 boards, ICS mixer NOT present */
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case 0x307: /* DRAMaccess */
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{
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uint8_t *adr;
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adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
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return *adr;
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}
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default:;
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}
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return 0xffff;
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}
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void gus_write(GUSEmuState * state, int port, int size, unsigned int data)
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{
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uint8_t *gusptr;
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gusptr = state->gusdatapos;
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GUSregd(portaccesses)++;
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switch (port & 0xff0f)
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{
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case 0x200: /* MixerCtrlReg */
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GUSregb(MixerCtrlReg2x0) = (uint8_t) data;
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break;
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case 0x206: /* IRQstatReg / SB2x6IRQ */
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if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */
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{
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GUSregb(TimerStatus2x8) |= 0x08;
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GUSregb(IRQStatReg2x6) = 0x10;
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GUS_irqrequest(state, state->gusirq, 1);
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}
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break;
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case 0x308: /* AdLib 388h */
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case 0x208: /* AdLibCommandReg */
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GUSregb(AdLibCommand2xA) = (uint8_t) data;
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break;
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case 0x309: /* AdLib 389h */
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case 0x209: /* AdLibDataReg */
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if ((GUSregb(AdLibCommand2xA) == 0x04) && (!(GUSregb(GUS45TimerCtrl) & 1))) /* GUS auto timer mode enabled? */
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{
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if (data & 0x80)
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GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */
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else
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GUSregb(TimerDataReg2x9) = (uint8_t) data;
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}
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else
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{
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GUSregb(AdLibData2x9) = (uint8_t) data;
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if (GUSregb(GUS45TimerCtrl) & 0x02)
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{
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GUSregb(TimerStatus2x8) |= 0x01;
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GUSregb(IRQStatReg2x6) = 0x10;
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GUS_irqrequest(state, state->gusirq, 1);
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}
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}
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break;
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case 0x20A:
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GUSregb(AdLibStatus2x8) = (uint8_t) data;
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break; /* AdLibStatus2x8 */
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case 0x20B: /* GUS hidden registers */
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switch (GUSregb(RegCtrl_2xF) & 0x7)
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{
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case 0:
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if (GUSregb(MixerCtrlReg2x0) & 0x40)
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GUSregb(IRQ_2xB) = (uint8_t) data; /* control register select bit */
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else
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GUSregb(DMA_2xB) = (uint8_t) data;
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break;
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/* case 1-4: general purpose emulation regs */
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case 5: /* clear stat reg 2xF */
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GUSregb(StatRead_2xF) = 0; /* ToDo: is this identical with GUS classic? */
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq);
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break;
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case 6: /* Jumper reg (Joystick/MIDI enable) */
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GUSregb(Jumper_2xB) = (uint8_t) data;
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break;
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default:;
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}
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break;
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case 0x20C: /* SB2xCd */
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if (GUSregb(GUS45TimerCtrl) & 0x20)
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{
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GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */
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GUSregb(IRQStatReg2x6) = 0x10;
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GUS_irqrequest(state, state->gusirq, 1);
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}
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/* fall through */
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case 0x20D: /* SB2xCd no IRQ */
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GUSregb(SB2xCd) = (uint8_t) data;
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break;
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case 0x20E: /* SB2xE */
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GUSregb(SB2xE) = (uint8_t) data;
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break;
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case 0x20F:
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GUSregb(RegCtrl_2xF) = (uint8_t) data;
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break; /* CtrlReg2xF */
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case 0x302: /* VoiceSelReg */
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GUSregb(VoiceSelReg3x2) = (uint8_t) data;
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break;
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case 0x303: /* FunkSelReg */
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GUSregb(FunkSelReg3x3) = (uint8_t) data;
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if ((uint8_t) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */
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{
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int voice;
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if (GUSregd(voicewavetableirq)) /* WavetableIRQ */
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{
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for (voice = 0; voice < 31; voice++)
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{
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if (GUSregd(voicewavetableirq) & (1 << voice))
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{
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GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */
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GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */
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if (!GUSregd(voicewavetableirq))
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GUSregb(IRQStatReg2x6) &= 0xdf;
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq);
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GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */
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return;
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}
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}
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}
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else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */
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{
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for (voice = 0; voice < 31; voice++)
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{
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if (GUSregd(voicevolrampirq) & (1 << voice))
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{
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GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */
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GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */
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if (!GUSregd(voicevolrampirq))
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GUSregb(IRQStatReg2x6) &= 0xbf;
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if (!GUSregb(IRQStatReg2x6))
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GUS_irqclear(state, state->gusirq);
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GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */
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return;
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}
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}
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}
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GUSregb(SynVoiceIRQ8f) = 0xe8; /* kein IRQ wartet */
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}
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break;
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case 0x304:
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case 0x305:
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{
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uint16_t writedata = (uint16_t) data;
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uint16_t readmask = 0x0000;
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if (size == 1)
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{
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readmask = 0xff00;
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writedata &= 0xff;
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if ((port & 0xff0f) == 0x305)
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{
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writedata = (uint16_t) (writedata << 8);
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readmask = 0x00ff;
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}
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}
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switch (GUSregb(FunkSelReg3x3))
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{
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/* voice specific functions */
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0c:
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case 0x0d:
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{
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int offset;
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if (!(GUSregb(GUS4cReset) & 0x01))
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break; /* reset flag active? */
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offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
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offset += (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Funktion*2 */
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GUSregw(offset) = (uint16_t) ((GUSregw(offset) & readmask) | writedata);
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}
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break;
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/* voice unspecific functions */
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case 0x0e: /* NumVoices */
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GUSregb(NumVoices) = (uint8_t) data;
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break;
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/* case 0x0f: */ /* read only */
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/* common functions */
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case 0x41: /* DramDMAContrReg */
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GUSregb(GUS41DMACtrl) = (uint8_t) data;
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if (data & 0x01)
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GUS_dmarequest(state);
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break;
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case 0x42: /* DramDMAmemPosReg */
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GUSregw(GUS42DMAStart) = (GUSregw(GUS42DMAStart) & readmask) | writedata;
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GUSregb(GUS50DMAHigh) &= 0xf; /* compatibility stuff... */
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break;
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case 0x43: /* DRAMaddrLo */
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GUSregd(GUSDRAMPOS24bit) =
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(GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | writedata;
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break;
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case 0x44: /* DRAMaddrHi */
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GUSregd(GUSDRAMPOS24bit) =
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(GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) << 16);
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break;
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case 0x45: /* TCtrlReg */
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GUSregb(GUS45TimerCtrl) = (uint8_t) data;
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if (!(data & 0x20))
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GUSregb(TimerStatus2x8) &= 0xe7; /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */
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if (!(data & 0x02))
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GUSregb(TimerStatus2x8) &= 0xfe; /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */
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if (!(GUSregb(TimerStatus2x8) & 0x19))
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GUSregb(IRQStatReg2x6) &= 0xef; /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared */
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/* catch up delayed timer IRQs: */
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if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) & 3))
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{
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if (GUSregb(TimerDataReg2x9) & 1) /* start timer 1 (80us decrement rate) */
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{
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if (!(GUSregb(TimerDataReg2x9) & 0x40))
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GUSregb(TimerStatus2x8) |= 0xc0; /* maskable bits */
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if (data & 4) /* timer1 irq enable */
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{
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GUSregb(TimerStatus2x8) |= 4; /* nonmaskable bit */
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GUSregb(IRQStatReg2x6) |= 4; /* timer 1 irq pending */
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}
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}
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if (GUSregb(TimerDataReg2x9) & 2) /* start timer 2 (320us decrement rate) */
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{
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if (!(GUSregb(TimerDataReg2x9) & 0x20))
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GUSregb(TimerStatus2x8) |= 0xa0; /* maskable bits */
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if (data & 8) /* timer2 irq enable */
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{
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GUSregb(TimerStatus2x8) |= 2; /* nonmaskable bit */
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GUSregb(IRQStatReg2x6) |= 8; /* timer 2 irq pending */
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}
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}
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GUSregw(TimerIRQs)--;
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if (GUSregw(BusyTimerIRQs) > 1)
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GUSregw(BusyTimerIRQs)--;
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else
|
|
GUSregw(BusyTimerIRQs) =
|
|
GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));
|
|
}
|
|
else
|
|
GUSregw(TimerIRQs) = 0;
|
|
|
|
if (!(data & 0x04))
|
|
{
|
|
GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */
|
|
GUSregb(IRQStatReg2x6) &= 0xfb;
|
|
}
|
|
if (!(data & 0x08))
|
|
{
|
|
GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */
|
|
GUSregb(IRQStatReg2x6) &= 0xf7;
|
|
}
|
|
if (!GUSregb(IRQStatReg2x6))
|
|
GUS_irqclear(state, state->gusirq);
|
|
break;
|
|
case 0x46: /* Counter1 */
|
|
GUSregb(GUS46Counter1) = (uint8_t) data;
|
|
break;
|
|
case 0x47: /* Counter2 */
|
|
GUSregb(GUS47Counter2) = (uint8_t) data;
|
|
break;
|
|
/* case 0x48: */ /* sampling freq reg not emulated (same as interwave) */
|
|
case 0x49: /* SampCtrlReg */
|
|
GUSregb(GUS49SampCtrl) = (uint8_t) data;
|
|
break;
|
|
/* case 0x4b: */ /* joystick trim not emulated */
|
|
case 0x4c: /* GUSreset */
|
|
GUSregb(GUS4cReset) = (uint8_t) data;
|
|
if (!(GUSregb(GUS4cReset) & 1)) /* reset... */
|
|
{
|
|
GUSregd(voicewavetableirq) = 0;
|
|
GUSregd(voicevolrampirq) = 0;
|
|
GUSregw(TimerIRQs) = 0;
|
|
GUSregw(BusyTimerIRQs) = 0;
|
|
GUSregb(NumVoices) = 0xcd;
|
|
GUSregb(IRQStatReg2x6) = 0;
|
|
GUSregb(TimerStatus2x8) = 0;
|
|
GUSregb(AdLibData2x9) = 0;
|
|
GUSregb(TimerDataReg2x9) = 0;
|
|
GUSregb(GUS41DMACtrl) = 0;
|
|
GUSregb(GUS45TimerCtrl) = 0;
|
|
GUSregb(GUS49SampCtrl) = 0;
|
|
GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */
|
|
GUS_irqclear(state, state->gusirq);
|
|
}
|
|
/* IRQ enable bit checked elsewhere */
|
|
/* EnableDAC bit may be used by external callers */
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case 0x307: /* DRAMaccess */
|
|
{
|
|
uint8_t *adr;
|
|
adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
|
|
*adr = (uint8_t) data;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Attention when breaking up a single DMA transfer to multiple ones:
|
|
* it may lead to multiple terminal count interrupts and broken transfers:
|
|
*
|
|
* 1. Whenever you transfer a piece of data, the gusemu callback is invoked
|
|
* 2. The callback may generate a TC irq (if the register was set up to do so)
|
|
* 3. The irq may result in the program using the GUS to reprogram the GUS
|
|
*
|
|
* Some programs also decide to upload by just checking if TC occurs
|
|
* (via interrupt or a cleared GUS dma flag)
|
|
* and then start the next transfer, without checking DMA state
|
|
*
|
|
* Thus: Always make sure to set the TC flag correctly!
|
|
*
|
|
* Note that the genuine GUS had a granularity of 16 bytes/words for low/high DMA
|
|
* while later cards had atomic granularity provided by an additional GUS50DMAHigh register
|
|
* GUSemu also uses this register to support byte-granular transfers for better compatibility
|
|
* with emulators other than GUSemu32
|
|
*/
|
|
|
|
void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int count, int TC)
|
|
{
|
|
/* this function gets called by the callback function as soon as a DMA transfer is about to start
|
|
* dma_addr is a translated address within accessible memory, not the physical one,
|
|
* count is (real dma count register)+1
|
|
* note that the amount of bytes transferred is fully determined by values in the DMA registers
|
|
* do not forget to update DMA states after transferring the entire block:
|
|
* DREQ cleared & TC asserted after the _whole_ transfer */
|
|
|
|
char *srcaddr;
|
|
char *destaddr;
|
|
char msbmask = 0;
|
|
uint8_t *gusptr;
|
|
gusptr = state->gusdatapos;
|
|
|
|
srcaddr = dma_addr; /* system memory address */
|
|
{
|
|
int offset = (GUSregw(GUS42DMAStart) << 4) + (GUSregb(GUS50DMAHigh) & 0xf);
|
|
if (state->gusdma >= 4)
|
|
offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */
|
|
destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */
|
|
}
|
|
|
|
GUSregw(GUS42DMAStart) += (uint16_t) (count >> 4); /* ToDo: add 16bit GUS page limit? */
|
|
GUSregb(GUS50DMAHigh) = (uint8_t) ((count + GUSregb(GUS50DMAHigh)) & 0xf); /* ToDo: add 16bit GUS page limit? */
|
|
|
|
if (GUSregb(GUS41DMACtrl) & 0x02) /* direction, 0 := sysram->gusram */
|
|
{
|
|
char *tmpaddr = destaddr;
|
|
destaddr = srcaddr;
|
|
srcaddr = tmpaddr;
|
|
}
|
|
|
|
if ((GUSregb(GUS41DMACtrl) & 0x80) && (!(GUSregb(GUS41DMACtrl) & 0x02)))
|
|
msbmask = (const char) 0x80; /* invert MSB */
|
|
for (; count > 0; count--)
|
|
{
|
|
if (GUSregb(GUS41DMACtrl) & 0x40)
|
|
*(destaddr++) = *(srcaddr++); /* 16 bit lobyte */
|
|
else
|
|
*(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 8 bit */
|
|
if (state->gusdma >= 4)
|
|
*(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 16 bit hibyte */
|
|
}
|
|
|
|
if (TC)
|
|
{
|
|
(GUSregb(GUS41DMACtrl)) &= 0xfe; /* clear DMA request bit */
|
|
if (GUSregb(GUS41DMACtrl) & 0x20) /* DMA terminal count IRQ */
|
|
{
|
|
GUSregb(IRQStatReg2x6) |= 0x80;
|
|
GUS_irqrequest(state, state->gusirq, 1);
|
|
}
|
|
}
|
|
}
|