469 lines
13 KiB
C
469 lines
13 KiB
C
/*
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* QEMU Freescale eTSEC Emulator
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*
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* Copyright (c) 2011-2013 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/ptimer.h"
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#include "hw/qdev-properties.h"
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#include "etsec.h"
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#include "registers.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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/* #define HEX_DUMP */
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/* #define DEBUG_REGISTER */
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#ifdef DEBUG_REGISTER
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static const int debug_etsec = 1;
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#else
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static const int debug_etsec;
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#endif
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#define DPRINTF(fmt, ...) do { \
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if (debug_etsec) { \
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qemu_log(fmt , ## __VA_ARGS__); \
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} \
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} while (0)
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/* call after any change to IEVENT or IMASK */
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void etsec_update_irq(eTSEC *etsec)
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{
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uint32_t ievent = etsec->regs[IEVENT].value;
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uint32_t imask = etsec->regs[IMASK].value;
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uint32_t active = ievent & imask;
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int tx = !!(active & IEVENT_TX_MASK);
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int rx = !!(active & IEVENT_RX_MASK);
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int err = !!(active & IEVENT_ERR_MASK);
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DPRINTF("%s IRQ ievent=%"PRIx32" imask=%"PRIx32" %c%c%c",
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__func__, ievent, imask,
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tx ? 'T' : '_',
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rx ? 'R' : '_',
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err ? 'E' : '_');
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qemu_set_irq(etsec->tx_irq, tx);
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qemu_set_irq(etsec->rx_irq, rx);
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qemu_set_irq(etsec->err_irq, err);
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}
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static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
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{
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eTSEC *etsec = opaque;
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uint32_t reg_index = addr / 4;
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eTSEC_Register *reg = NULL;
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uint32_t ret = 0x0;
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assert(reg_index < ETSEC_REG_NUMBER);
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reg = &etsec->regs[reg_index];
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switch (reg->access) {
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case ACC_WO:
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ret = 0x00000000;
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break;
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case ACC_RW:
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case ACC_W1C:
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case ACC_RO:
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default:
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ret = reg->value;
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break;
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}
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DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx
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" : %s (%s)\n",
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ret, addr, reg->name, reg->desc);
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return ret;
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}
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static void write_tstat(eTSEC *etsec,
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eTSEC_Register *reg,
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uint32_t reg_index,
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uint32_t value)
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{
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int i = 0;
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for (i = 0; i < 8; i++) {
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/* Check THLTi flag in TSTAT */
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if (value & (1 << (31 - i))) {
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etsec_walk_tx_ring(etsec, i);
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}
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}
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/* Write 1 to clear */
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reg->value &= ~value;
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}
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static void write_rstat(eTSEC *etsec,
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eTSEC_Register *reg,
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uint32_t reg_index,
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uint32_t value)
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{
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int i = 0;
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for (i = 0; i < 8; i++) {
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/* Check QHLTi flag in RSTAT */
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if (value & (1 << (23 - i)) && !(reg->value & (1 << (23 - i)))) {
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etsec_walk_rx_ring(etsec, i);
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}
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}
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/* Write 1 to clear */
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reg->value &= ~value;
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}
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static void write_tbasex(eTSEC *etsec,
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eTSEC_Register *reg,
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uint32_t reg_index,
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uint32_t value)
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{
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reg->value = value & ~0x7;
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/* Copy this value in the ring's TxBD pointer */
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etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;
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}
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static void write_rbasex(eTSEC *etsec,
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eTSEC_Register *reg,
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uint32_t reg_index,
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uint32_t value)
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{
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reg->value = value & ~0x7;
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/* Copy this value in the ring's RxBD pointer */
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etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
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}
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static void write_dmactrl(eTSEC *etsec,
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eTSEC_Register *reg,
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uint32_t reg_index,
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uint32_t value)
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{
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reg->value = value;
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if (value & DMACTRL_GRS) {
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if (etsec->rx_buffer_len != 0) {
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/* Graceful receive stop delayed until end of frame */
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} else {
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/* Graceful receive stop now */
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etsec->regs[IEVENT].value |= IEVENT_GRSC;
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etsec_update_irq(etsec);
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}
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}
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if (value & DMACTRL_GTS) {
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if (etsec->tx_buffer_len != 0) {
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/* Graceful transmit stop delayed until end of frame */
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} else {
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/* Graceful transmit stop now */
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etsec->regs[IEVENT].value |= IEVENT_GTSC;
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etsec_update_irq(etsec);
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}
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}
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if (!(value & DMACTRL_WOP)) {
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/* Start polling */
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ptimer_transaction_begin(etsec->ptimer);
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ptimer_stop(etsec->ptimer);
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ptimer_set_count(etsec->ptimer, 1);
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ptimer_run(etsec->ptimer, 1);
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ptimer_transaction_commit(etsec->ptimer);
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}
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}
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static void etsec_write(void *opaque,
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hwaddr addr,
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uint64_t value,
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unsigned size)
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{
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eTSEC *etsec = opaque;
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uint32_t reg_index = addr / 4;
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eTSEC_Register *reg = NULL;
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uint32_t before = 0x0;
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assert(reg_index < ETSEC_REG_NUMBER);
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reg = &etsec->regs[reg_index];
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before = reg->value;
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switch (reg_index) {
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case IEVENT:
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/* Write 1 to clear */
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reg->value &= ~value;
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etsec_update_irq(etsec);
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break;
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case IMASK:
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reg->value = value;
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etsec_update_irq(etsec);
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break;
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case DMACTRL:
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write_dmactrl(etsec, reg, reg_index, value);
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break;
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case TSTAT:
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write_tstat(etsec, reg, reg_index, value);
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break;
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case RSTAT:
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write_rstat(etsec, reg, reg_index, value);
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break;
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case TBASE0 ... TBASE7:
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write_tbasex(etsec, reg, reg_index, value);
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break;
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case RBASE0 ... RBASE7:
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write_rbasex(etsec, reg, reg_index, value);
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break;
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case MIIMCFG ... MIIMIND:
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etsec_write_miim(etsec, reg, reg_index, value);
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break;
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default:
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/* Default handling */
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switch (reg->access) {
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case ACC_RW:
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case ACC_WO:
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reg->value = value;
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break;
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case ACC_W1C:
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reg->value &= ~value;
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break;
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case ACC_RO:
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default:
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/* Read Only or Unknown register */
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break;
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}
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}
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DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
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" val:0x%08x->0x%08x : %s (%s)\n",
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(unsigned int)value, addr, before, reg->value,
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reg->name, reg->desc);
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}
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static const MemoryRegionOps etsec_ops = {
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.read = etsec_read,
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.write = etsec_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void etsec_timer_hit(void *opaque)
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{
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eTSEC *etsec = opaque;
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ptimer_stop(etsec->ptimer);
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if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {
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if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {
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etsec_walk_tx_ring(etsec, 0);
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}
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ptimer_set_count(etsec->ptimer, 1);
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ptimer_run(etsec->ptimer, 1);
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}
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}
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static void etsec_reset(DeviceState *d)
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{
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eTSEC *etsec = ETSEC_COMMON(d);
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int i = 0;
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int reg_index = 0;
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/* Default value for all registers */
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for (i = 0; i < ETSEC_REG_NUMBER; i++) {
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etsec->regs[i].name = "Reserved";
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etsec->regs[i].desc = "";
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etsec->regs[i].access = ACC_UNKNOWN;
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etsec->regs[i].value = 0x00000000;
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}
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/* Set-up known registers */
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for (i = 0; eTSEC_registers_def[i].name != NULL; i++) {
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reg_index = eTSEC_registers_def[i].offset / 4;
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etsec->regs[reg_index].name = eTSEC_registers_def[i].name;
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etsec->regs[reg_index].desc = eTSEC_registers_def[i].desc;
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etsec->regs[reg_index].access = eTSEC_registers_def[i].access;
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etsec->regs[reg_index].value = eTSEC_registers_def[i].reset;
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}
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etsec->tx_buffer = NULL;
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etsec->tx_buffer_len = 0;
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etsec->rx_buffer = NULL;
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etsec->rx_buffer_len = 0;
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etsec->phy_status =
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MII_SR_EXTENDED_CAPS | MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS |
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MII_SR_AUTONEG_COMPLETE | MII_SR_PREAMBLE_SUPPRESS |
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MII_SR_EXTENDED_STATUS | MII_SR_100T2_HD_CAPS | MII_SR_100T2_FD_CAPS |
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MII_SR_10T_HD_CAPS | MII_SR_10T_FD_CAPS | MII_SR_100X_HD_CAPS |
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MII_SR_100X_FD_CAPS | MII_SR_100T4_CAPS;
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etsec_update_irq(etsec);
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}
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static ssize_t etsec_receive(NetClientState *nc,
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const uint8_t *buf,
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size_t size)
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{
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ssize_t ret;
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eTSEC *etsec = qemu_get_nic_opaque(nc);
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#if defined(HEX_DUMP)
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fprintf(stderr, "%s receive size:%zd\n", nc->name, size);
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qemu_hexdump((void *)buf, stderr, "", size);
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#endif
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/* Flush is unnecessary as are already in receiving path */
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etsec->need_flush = false;
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ret = etsec_rx_ring_write(etsec, buf, size);
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if (ret == 0) {
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/* The packet will be queued, let's flush it when buffer is available
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* again. */
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etsec->need_flush = true;
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}
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return ret;
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}
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static void etsec_set_link_status(NetClientState *nc)
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{
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eTSEC *etsec = qemu_get_nic_opaque(nc);
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etsec_miim_link_status(etsec, nc);
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}
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static NetClientInfo net_etsec_info = {
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.type = NET_CLIENT_DRIVER_NIC,
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.size = sizeof(NICState),
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.receive = etsec_receive,
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.link_status_changed = etsec_set_link_status,
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};
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static void etsec_realize(DeviceState *dev, Error **errp)
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{
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eTSEC *etsec = ETSEC_COMMON(dev);
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etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
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object_get_typename(OBJECT(dev)), dev->id, etsec);
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qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);
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etsec->ptimer = ptimer_init(etsec_timer_hit, etsec, PTIMER_POLICY_DEFAULT);
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ptimer_transaction_begin(etsec->ptimer);
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ptimer_set_freq(etsec->ptimer, 100);
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ptimer_transaction_commit(etsec->ptimer);
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}
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static void etsec_instance_init(Object *obj)
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{
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eTSEC *etsec = ETSEC_COMMON(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,
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"eTSEC", 0x1000);
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sysbus_init_mmio(sbd, &etsec->io_area);
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sysbus_init_irq(sbd, &etsec->tx_irq);
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sysbus_init_irq(sbd, &etsec->rx_irq);
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sysbus_init_irq(sbd, &etsec->err_irq);
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}
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static Property etsec_properties[] = {
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DEFINE_NIC_PROPERTIES(eTSEC, conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void etsec_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = etsec_realize;
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dc->reset = etsec_reset;
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device_class_set_props(dc, etsec_properties);
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/* Supported by ppce500 machine */
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dc->user_creatable = true;
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}
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static TypeInfo etsec_info = {
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.name = "eTSEC",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(eTSEC),
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.class_init = etsec_class_init,
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.instance_init = etsec_instance_init,
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};
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static void etsec_register_types(void)
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{
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type_register_static(&etsec_info);
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}
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type_init(etsec_register_types)
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DeviceState *etsec_create(hwaddr base,
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MemoryRegion * mr,
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NICInfo * nd,
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qemu_irq tx_irq,
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qemu_irq rx_irq,
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qemu_irq err_irq)
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{
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DeviceState *dev;
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dev = qdev_new("eTSEC");
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qdev_set_nic_properties(dev, nd);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);
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memory_region_add_subregion(mr, base,
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SYS_BUS_DEVICE(dev)->mmio[0].memory);
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return dev;
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}
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