c0a55a0c9d
Some SDHCI IP can be synthetized in various endianness: https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. Our current implementation is little-endian. In order to support big endianness: - Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le') - Add an 'endianness' property to SDHCIState (default little endian) - Set the 'io_ops' field in realize() after checking the property - Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221101222934.52444-3-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> |
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| .. | ||
| allwinner-sdhost.c | ||
| aspeed_sdhci.c | ||
| bcm2835_sdhost.c | ||
| cadence_sdhci.c | ||
| core.c | ||
| Kconfig | ||
| meson.build | ||
| npcm7xx_sdhci.c | ||
| omap_mmc.c | ||
| pl181.c | ||
| pxa2xx_mmci.c | ||
| sd.c | ||
| sdhci-internal.h | ||
| sdhci-pci.c | ||
| sdhci.c | ||
| sdmmc-internal.c | ||
| sdmmc-internal.h | ||
| ssi-sd.c | ||
| trace-events | ||
| trace.h | ||