44423107e7
- add NMI support; - add DFPU option implementation; - update FPU tests to support both FPU2000 and DFPU; - add example cores with FPU2000 and DFPU. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAl9AKgETHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRHjID/wJbhb8AyiCSXNbUZWRr8tOVqYjLm3I RJjiXC1rxHcUIod6OQjUyrr8exzaR9zQazI1oBJtOCFtlQeBgfC3r6T74QnLMb7F 0dhQ1CseiTl0kecJqcDfhl8Y4FtUshMeu91+jwlff68mS1BFYdZVWDstmB1HeDfN xkxOD0I4/Ppkpu82UhCKJ9WhTtuBa0/krtgOaUQNWBXEmFtMGJb4mrZT+Ph2Tw25 9+LNPluyJ6ZrTDjDOMBsOReXqpz/I+1JbyOZ1Z0i8LzqOFfpGixN17BxSBc/j59V sb+xrZjKb/V1jJWJX31feQhwHPK2OHzmTUfx3JzUDh+Y8TNG8s7XtsA2BYX0vV8F Zm9107KbKOvF7wJ52g+cXp2EbFquje4/q6QoH7mQ9iXgXoXeTTUwXHxfIXzmIgqP Raj2evTWK0r1P/jzGaBFKqBoQ7ixGIJELQHJaTckYDK71oICSPYzp9A/iNr1a7Sh xvgU9KhAt3cWDRAa6apup5bk/mwHlr71Ue4w0pk3WG46Zry1Qiti/nSD8v7gTKTs oNGbYiZgQXAIw9V2m/UZgN3BEQI7Y4vr889LCySEhhYkVWFvhHIVjYYZFJ8KVtGs LH5Nlm904Ix3piU7I41pISe8DeD7VhW1QpSD5BIpBMnsftXun9y/bF8sR67PV36J xSht7off0nw7/g== =8N7r -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging target/xtensa updates for 5.2: - add NMI support; - add DFPU option implementation; - update FPU tests to support both FPU2000 and DFPU; - add example cores with FPU2000 and DFPU. # gpg: Signature made Fri 21 Aug 2020 21:09:37 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20200821-xtensa: (24 commits) target/xtensa: import DSP3400 core target/xtensa: import de233_fpu core tests/tcg/xtensa: add DFP0 arithmetic tests tests/tcg/xtensa: test double precision load/store tests/tcg/xtensa: add fp0 div and sqrt tests tests/tcg/xtensa: update test_lsc for DFPU tests/tcg/xtensa: update test_fp1 for DFPU tests/tcg/xtensa: update test_fp0_conv for DFPU tests/tcg/xtensa: expand madd tests tests/tcg/xtensa: update test_fp0_arith for DFPU tests/tcg/xtensa: fix test execution on ISS target/xtensa: implement FPU division and square root target/xtensa: add DFPU registers and opcodes target/xtensa: add DFPU option target/xtensa: don't access BR regfile directly target/xtensa: move FSR/FCR register accessors target/xtensa: rename FPU2000 translators and helpers target/xtensa: support copying registers up to 64 bits wide target/xtensa: add geometry to xtensa_get_regfile_by_name softfloat: add xtensa specialization for pickNaNMulAdd ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| alpha | ||
| arm | ||
| avr | ||
| cris | ||
| hppa | ||
| i386 | ||
| lm32 | ||
| m68k | ||
| microblaze | ||
| mips | ||
| moxie | ||
| nios2 | ||
| openrisc | ||
| ppc | ||
| riscv | ||
| rx | ||
| s390x | ||
| sh4 | ||
| sparc | ||
| tilegx | ||
| tricore | ||
| unicore32 | ||
| xtensa | ||
| meson.build | ||