KONRAD Frederic b3e8692918 gdbstub: riscv: fix the fflags registers ... While debugging an application with GDB the following might happen: (gdb) return Make xxx return now? (y or n) y Could not fetch register "fflags"; remote failure reply 'E14' This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr number (8). It should use the csr_register_map in order to reach the riscv_cpu_get_fflags callback. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-09-17 08:42:50 -07:00
..
insn_trans	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
cpu_bits.h	target/riscv: Update the Hypervisor CSRs to v0.4	2019-09-17 08:42:43 -07:00
cpu_helper.c	riscv: rv32: Root page table address can be larger than 32-bit	2019-09-17 08:42:43 -07:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu.c	target/riscv: Use both register name and ABI name	2019-09-17 08:42:50 -07:00
cpu.h	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point	2019-09-17 08:42:50 -07:00
csr.c	target/riscv: Fix mstatus dirty mask	2019-09-17 08:42:50 -07:00
fpu_helper.c	target/riscv: rationalise softfloat includes	2019-08-19 12:07:13 +01:00
gdbstub.c	gdbstub: riscv: fix the fflags registers	2019-09-17 08:42:50 -07:00
helper.h
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode
insn32.decode
instmap.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
Makefile.objs	riscv: hmp: Add a command to show virtual memory mappings	2019-09-17 08:42:43 -07:00
monitor.c	riscv: hmp: Add a command to show virtual memory mappings	2019-09-17 08:42:43 -07:00
op_helper.c	target/riscv: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
pmp.c	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	2019-09-17 08:42:42 -07:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-06-23 23:44:41 -07:00
trace-events	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	2019-09-17 08:42:42 -07:00
translate.c	target/riscv: Remove redundant declaration pragmas	2019-08-19 08:13:14 -07:00