8905770b27
G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
441 lines
14 KiB
C
441 lines
14 KiB
C
/*
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* MicroBlaze virtual CPU header
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*
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* Copyright (c) 2009 Edgar E. Iglesias
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef MICROBLAZE_CPU_H
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#define MICROBLAZE_CPU_H
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#include "qemu/cpu-float.h"
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typedef struct CPUArchState CPUMBState;
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#if !defined(CONFIG_USER_ONLY)
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#include "mmu.h"
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#endif
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#define EXCP_MMU 1
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#define EXCP_IRQ 2
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#define EXCP_SYSCALL 3 /* user-only */
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#define EXCP_HW_BREAK 4
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#define EXCP_HW_EXCP 5
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/* MicroBlaze-specific interrupt pending bits. */
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#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
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/* Meanings of the MBCPU object's two inbound GPIO lines */
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#define MB_CPU_IRQ 0
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#define MB_CPU_FIR 1
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/* Register aliases. R0 - R15 */
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#define R_SP 1
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#define SR_PC 0
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#define SR_MSR 1
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#define SR_EAR 3
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#define SR_ESR 5
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#define SR_FSR 7
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#define SR_BTR 0xb
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#define SR_EDR 0xd
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/* MSR flags. */
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#define MSR_BE (1<<0) /* 0x001 */
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#define MSR_IE (1<<1) /* 0x002 */
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#define MSR_C (1<<2) /* 0x004 */
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#define MSR_BIP (1<<3) /* 0x008 */
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#define MSR_FSL (1<<4) /* 0x010 */
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#define MSR_ICE (1<<5) /* 0x020 */
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#define MSR_DZ (1<<6) /* 0x040 */
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#define MSR_DCE (1<<7) /* 0x080 */
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#define MSR_EE (1<<8) /* 0x100 */
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#define MSR_EIP (1<<9) /* 0x200 */
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#define MSR_PVR (1<<10) /* 0x400 */
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#define MSR_CC (1<<31)
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/* Machine State Register (MSR) Fields */
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#define MSR_UM (1<<11) /* User Mode */
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#define MSR_UMS (1<<12) /* User Mode Save */
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#define MSR_VM (1<<13) /* Virtual Mode */
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#define MSR_VMS (1<<14) /* Virtual Mode Save */
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#define MSR_KERNEL MSR_EE|MSR_VM
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//#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
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#define MSR_KERNEL_VMS MSR_EE|MSR_VMS
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//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
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/* Exception State Register (ESR) Fields */
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#define ESR_DIZ (1<<11) /* Zone Protection */
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#define ESR_W (1<<11) /* Unaligned word access */
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#define ESR_S (1<<10) /* Store instruction */
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#define ESR_ESS_FSL_OFFSET 5
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#define ESR_ESS_MASK (0x7f << 5)
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#define ESR_EC_FSL 0
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#define ESR_EC_UNALIGNED_DATA 1
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#define ESR_EC_ILLEGAL_OP 2
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#define ESR_EC_INSN_BUS 3
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#define ESR_EC_DATA_BUS 4
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#define ESR_EC_DIVZERO 5
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#define ESR_EC_FPU 6
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#define ESR_EC_PRIVINSN 7
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#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
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#define ESR_EC_DATA_STORAGE 8
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#define ESR_EC_INSN_STORAGE 9
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#define ESR_EC_DATA_TLB 10
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#define ESR_EC_INSN_TLB 11
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#define ESR_EC_MASK 31
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/* Floating Point Status Register (FSR) Bits */
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#define FSR_IO (1<<4) /* Invalid operation */
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#define FSR_DZ (1<<3) /* Divide-by-zero */
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#define FSR_OF (1<<2) /* Overflow */
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#define FSR_UF (1<<1) /* Underflow */
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#define FSR_DO (1<<0) /* Denormalized operand error */
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/* Version reg. */
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/* Basic PVR mask */
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#define PVR0_PVR_FULL_MASK 0x80000000
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#define PVR0_USE_BARREL_MASK 0x40000000
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#define PVR0_USE_DIV_MASK 0x20000000
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#define PVR0_USE_HW_MUL_MASK 0x10000000
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#define PVR0_USE_FPU_MASK 0x08000000
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#define PVR0_USE_EXC_MASK 0x04000000
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#define PVR0_USE_ICACHE_MASK 0x02000000
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#define PVR0_USE_DCACHE_MASK 0x01000000
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#define PVR0_USE_MMU_MASK 0x00800000
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#define PVR0_USE_BTC 0x00400000
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#define PVR0_ENDI_MASK 0x00200000
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#define PVR0_FAULT 0x00100000
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#define PVR0_VERSION_MASK 0x0000FF00
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#define PVR0_USER1_MASK 0x000000FF
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#define PVR0_SPROT_MASK 0x00000001
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#define PVR0_VERSION_SHIFT 8
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/* User 2 PVR mask */
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#define PVR1_USER2_MASK 0xFFFFFFFF
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/* Configuration PVR masks */
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#define PVR2_D_OPB_MASK 0x80000000
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#define PVR2_D_LMB_MASK 0x40000000
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#define PVR2_I_OPB_MASK 0x20000000
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#define PVR2_I_LMB_MASK 0x10000000
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#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
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#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
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#define PVR2_D_PLB_MASK 0x02000000 /* new */
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#define PVR2_I_PLB_MASK 0x01000000 /* new */
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#define PVR2_INTERCONNECT 0x00800000 /* new */
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#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
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#define PVR2_USE_FSL_EXC 0x00040000 /* new */
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#define PVR2_USE_MSR_INSTR 0x00020000
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#define PVR2_USE_PCMP_INSTR 0x00010000
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#define PVR2_AREA_OPTIMISED 0x00008000
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#define PVR2_USE_BARREL_MASK 0x00004000
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#define PVR2_USE_DIV_MASK 0x00002000
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#define PVR2_USE_HW_MUL_MASK 0x00001000
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#define PVR2_USE_FPU_MASK 0x00000800
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#define PVR2_USE_MUL64_MASK 0x00000400
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#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
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#define PVR2_USE_IPLBEXC 0x00000100
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#define PVR2_USE_DPLBEXC 0x00000080
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#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
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#define PVR2_UNALIGNED_EXC_MASK 0x00000020
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#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
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#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
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#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
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#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
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#define PVR2_FPU_EXC_MASK 0x00000001
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/* Debug and exception PVR masks */
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#define PVR3_DEBUG_ENABLED_MASK 0x80000000
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#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
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#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
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#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
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#define PVR3_FSL_LINKS_MASK 0x00000380
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/* ICache config PVR masks */
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#define PVR4_USE_ICACHE_MASK 0x80000000
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#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
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#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
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#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
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#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
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/* DCache config PVR masks */
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#define PVR5_USE_DCACHE_MASK 0x80000000
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#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
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#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
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#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
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#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
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#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
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/* ICache base address PVR mask */
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#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
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/* ICache high address PVR mask */
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#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* DCache base address PVR mask */
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#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
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/* DCache high address PVR mask */
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#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* Target family PVR mask */
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#define PVR10_TARGET_FAMILY_MASK 0xFF000000
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#define PVR10_ASIZE_SHIFT 18
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/* MMU descrtiption */
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#define PVR11_USE_MMU 0xC0000000
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#define PVR11_MMU_ITLB_SIZE 0x38000000
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#define PVR11_MMU_DTLB_SIZE 0x07000000
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#define PVR11_MMU_TLB_ACCESS 0x00C00000
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#define PVR11_MMU_ZONES 0x003E0000
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/* MSR Reset value PVR mask */
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#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
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#define C_PVR_NONE 0
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#define C_PVR_BASIC 1
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#define C_PVR_FULL 2
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/* CPU flags. */
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/* Condition codes. */
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#define CC_GE 5
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#define CC_GT 4
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#define CC_LE 3
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#define CC_LT 2
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#define CC_NE 1
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#define CC_EQ 0
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#define STREAM_EXCEPTION (1 << 0)
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#define STREAM_ATOMIC (1 << 1)
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#define STREAM_TEST (1 << 2)
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#define STREAM_CONTROL (1 << 3)
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#define STREAM_NONBLOCK (1 << 4)
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#define TARGET_INSN_START_EXTRA_WORDS 1
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/* use-non-secure property masks */
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#define USE_NON_SECURE_M_AXI_DP_MASK 0x1
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#define USE_NON_SECURE_M_AXI_IP_MASK 0x2
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#define USE_NON_SECURE_M_AXI_DC_MASK 0x4
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#define USE_NON_SECURE_M_AXI_IC_MASK 0x8
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struct CPUArchState {
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uint32_t bvalue; /* TCG temporary, only valid during a TB */
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uint32_t btarget; /* Full resolved branch destination */
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uint32_t imm;
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uint32_t regs[32];
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uint32_t pc;
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uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */
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uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */
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target_ulong ear;
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uint32_t esr;
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uint32_t fsr;
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uint32_t btr;
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uint32_t edr;
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float_status fp_status;
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/* Stack protectors. Yes, it's a hw feature. */
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uint32_t slr, shr;
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/* lwx/swx reserved address */
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#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
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target_ulong res_addr;
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uint32_t res_val;
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/* Internal flags. */
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#define IMM_FLAG (1 << 0)
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#define BIMM_FLAG (1 << 1)
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#define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */
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/* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flags */
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/* MSR_UM (1 << 11) */
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/* MSR_VM (1 << 13) */
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/* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */
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#define D_FLAG (1 << 12) /* Bit in ESR. */
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#define DRTI_FLAG (1 << 16)
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#define DRTE_FLAG (1 << 17)
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#define DRTB_FLAG (1 << 18)
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/* TB dependent CPUMBState. */
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#define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \
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DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
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#define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE)
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uint32_t iflags;
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#if !defined(CONFIG_USER_ONLY)
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/* Unified MMU. */
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MicroBlazeMMU mmu;
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#endif
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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/* These fields are preserved on reset. */
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};
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/*
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* Microblaze Configuration Settings
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*
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* Note that the structure is sorted by type and size to minimize holes.
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*/
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typedef struct {
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char *version;
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uint64_t addr_mask;
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uint32_t base_vectors;
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uint32_t pvr_user2;
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uint32_t pvr_regs[13];
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uint8_t addr_size;
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uint8_t use_fpu;
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uint8_t use_hw_mul;
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uint8_t pvr_user1;
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uint8_t pvr;
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uint8_t mmu;
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uint8_t mmu_tlb_access;
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uint8_t mmu_zones;
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bool stackprot;
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bool use_barrel;
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bool use_div;
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bool use_msr_instr;
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bool use_pcmp_instr;
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bool use_mmu;
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uint8_t use_non_secure;
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bool dcache_writeback;
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bool endi;
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bool dopb_bus_exception;
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bool iopb_bus_exception;
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bool illegal_opcode_exception;
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bool opcode_0_illegal;
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bool div_zero_exception;
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bool unaligned_exceptions;
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} MicroBlazeCPUConfig;
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/**
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* MicroBlazeCPU:
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* @env: #CPUMBState
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*
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* A MicroBlaze CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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bool ns_axi_dp;
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bool ns_axi_ip;
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bool ns_axi_dc;
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bool ns_axi_ic;
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CPUNegativeOffsetState neg;
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CPUMBState env;
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MicroBlazeCPUConfig cfg;
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};
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#ifndef CONFIG_USER_ONLY
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void mb_cpu_do_interrupt(CPUState *cs);
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bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
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#endif /* !CONFIG_USER_ONLY */
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G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
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{
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/* Replicate MSR[C] to MSR[CC]. */
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return env->msr | (env->msr_c * (MSR_C | MSR_CC));
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}
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static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
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{
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env->msr_c = (val >> 2) & 1;
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/*
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* Clear both MSR[C] and MSR[CC] from the saved copy.
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* MSR_PVR is not writable and is always clear.
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*/
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env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR);
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}
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void mb_tcg_init(void);
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#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
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/* MMU modes definitions */
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#define MMU_NOMMU_IDX 0
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#define MMU_KERNEL_IDX 1
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#define MMU_USER_IDX 2
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/* See NB_MMU_MODES further up the file. */
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#include "exec/cpu-all.h"
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/* Ensure there is no overlap between the two masks. */
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QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
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static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
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*cs_base = (*flags & IMM_FLAG ? env->imm : 0);
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}
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#if !defined(CONFIG_USER_ONLY)
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bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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#endif
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static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
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{
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MicroBlazeCPU *cpu = env_archcpu(env);
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/* Are we in nommu mode?. */
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if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
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return MMU_NOMMU_IDX;
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}
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if (env->msr & MSR_UM) {
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return MMU_USER_IDX;
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}
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return MMU_KERNEL_IDX;
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}
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#ifndef CONFIG_USER_ONLY
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extern const VMStateDescription vmstate_mb_cpu;
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#endif
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#endif
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