qemu-e2k/target/openrisc
Richard Henderson 455d45d22c target/openrisc: Merge tlb allocation into CPUOpenRISCState
There is no reason to allocate this separately.  This was probably
copied from target/mips which makes the same mistake.

While doing so, move tlb into the clear-on-reset range.  While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03 00:05:28 +09:00
..
cpu.c target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
cpu.h target/openrisc: Merge tlb allocation into CPUOpenRISCState 2018-07-03 00:05:28 +09:00
disas.c target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
exception_helper.c misc: remove duplicated includes 2017-12-18 17:07:02 +03:00
exception.c
exception.h
fpu_helper.c target-openrisc: Write back result before FPE exception 2018-05-14 14:35:02 -07:00
gdbstub.c target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
helper.h target/openrisc: Form the spr index from tcg 2018-07-03 00:05:28 +09:00
insns.decode target/openrisc: Convert dec_float 2018-05-14 14:55:29 -07:00
interrupt_helper.c target/openrisc: Merge tlb allocation into CPUOpenRISCState 2018-07-03 00:05:28 +09:00
interrupt.c target/openrisc: Merge tlb allocation into CPUOpenRISCState 2018-07-03 00:05:28 +09:00
machine.c target/openrisc: Merge tlb allocation into CPUOpenRISCState 2018-07-03 00:05:28 +09:00
Makefile.objs target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
mmu_helper.c accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
mmu.c target/openrisc: Merge tlb allocation into CPUOpenRISCState 2018-07-03 00:05:28 +09:00
sys_helper.c target/openrisc: Merge tlb allocation into CPUOpenRISCState 2018-07-03 00:05:28 +09:00
translate.c target/openrisc: Form the spr index from tcg 2018-07-03 00:05:28 +09:00