7fe48483cd
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1110 c046a42c-6fe2-441c-8c8c-71466251a162
914 lines
27 KiB
C
914 lines
27 KiB
C
/*
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* PPC emulation helpers for qemu.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h"
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#if defined (USE_OPEN_FIRMWARE)
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#include <time.h>
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#include "of.h"
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#endif
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_EXCEPTIONS
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/*****************************************************************************/
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/* PPC MMU emulation */
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int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
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int is_user, int is_softmmu);
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/* Perform BAT hit & translation */
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static int get_bat (CPUState *env, uint32_t *real, int *prot,
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uint32_t virtual, int rw, int type)
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{
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uint32_t *BATlt, *BATut, *BATu, *BATl;
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uint32_t base, BEPIl, BEPIu, bl;
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int i;
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int ret = -1;
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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}
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#endif
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switch (type) {
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case ACCESS_CODE:
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BATlt = env->IBAT[1];
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BATut = env->IBAT[0];
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break;
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default:
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BATlt = env->DBAT[1];
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BATut = env->DBAT[0];
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break;
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}
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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}
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#endif
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base = virtual & 0xFFFC0000;
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for (i = 0; i < 4; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15;
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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*BATu, *BATl);
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}
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#endif
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if ((virtual & 0xF0000000) == BEPIu &&
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((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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/* BAT matches */
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if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
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(msr_pr == 1 && (*BATu & 0x00000001))) {
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/* Get physical address */
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*real = (*BATl & 0xF0000000) |
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((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
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(virtual & 0x0001F000);
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if (*BATl & 0x00000001)
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*prot = PAGE_READ;
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if (*BATl & 0x00000002)
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*prot = PAGE_WRITE | PAGE_READ;
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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i, *real, *prot & PAGE_READ ? 'R' : '-',
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*prot & PAGE_WRITE ? 'W' : '-');
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}
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#endif
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ret = 0;
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break;
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}
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}
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}
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if (ret < 0) {
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#if defined (DEBUG_BATS)
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printf("no BAT match for 0x%08x:\n", virtual);
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for (i = 0; i < 4; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15;
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printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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"0x%08x 0x%08x 0x%08x\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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}
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#endif
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}
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/* No hit */
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return ret;
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}
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/* PTE table lookup */
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static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
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int h, int key, int rw)
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{
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uint32_t pte0, pte1, keep = 0, access = 0;
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int i, good = -1, store = 0;
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int ret = -1; /* No entry found */
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for (i = 0; i < 8; i++) {
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pte0 = ldl_raw(phys_ram_base + base + (i * 8));
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pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
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"%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
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pte0 >> 31, h, (pte0 >> 6) & 1, va);
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}
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#endif
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/* Check validity and table match */
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if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
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/* Check vsid & api */
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if ((pte0 & 0x7FFFFFBF) == va) {
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if (good == -1) {
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good = i;
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keep = pte1;
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} else {
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/* All matches should have equal RPN, WIMG & PP */
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if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
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if (loglevel > 0)
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fprintf(logfile, "Bad RPN/WIMG/PP\n");
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return -1;
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}
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}
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/* Check access rights */
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if (key == 0) {
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access = PAGE_READ;
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if ((pte1 & 0x00000003) != 0x3)
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access |= PAGE_WRITE;
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} else {
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switch (pte1 & 0x00000003) {
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case 0x0:
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access = 0;
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break;
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case 0x1:
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case 0x3:
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access = PAGE_READ;
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break;
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case 0x2:
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access = PAGE_READ | PAGE_WRITE;
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break;
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}
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}
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if (ret < 0) {
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if ((rw == 0 && (access & PAGE_READ)) ||
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(rw == 1 && (access & PAGE_WRITE))) {
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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fprintf(logfile, "PTE access granted !\n");
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#endif
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good = i;
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keep = pte1;
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ret = 0;
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} else {
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/* Access right violation */
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ret = -2;
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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fprintf(logfile, "PTE access rejected\n");
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#endif
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}
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*prot = access;
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}
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}
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}
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}
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if (good != -1) {
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*RPN = keep & 0xFFFFF000;
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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*RPN, *prot, ret);
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}
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#endif
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/* Update page flags */
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if (!(keep & 0x00000100)) {
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/* Access flag */
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keep |= 0x00000100;
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store = 1;
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}
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if (!(keep & 0x00000080)) {
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if (rw && ret == 0) {
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/* Change flag */
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keep |= 0x00000080;
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store = 1;
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} else {
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/* Force page fault for first write access */
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*prot &= ~PAGE_WRITE;
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}
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}
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if (store) {
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stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
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}
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}
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return ret;
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}
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static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
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{
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return (sdr1 & 0xFFFF0000) | (hash & mask);
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}
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/* Perform segment based translation */
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static int get_segment (CPUState *env, uint32_t *real, int *prot,
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uint32_t virtual, int rw, int type)
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{
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uint32_t pg_addr, sdr, ptem, vsid, pgidx;
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uint32_t hash, mask;
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uint32_t sr;
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int key;
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int ret = -1, ret2;
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sr = env->sr[virtual >> 28];
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
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"lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
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virtual, virtual >> 28, sr, env->nip,
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env->lr, msr_ir, msr_dr, msr_pr, rw, type);
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}
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#endif
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key = (((sr & 0x20000000) && msr_pr == 1) ||
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((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
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if ((sr & 0x80000000) == 0) {
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
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key, sr & 0x10000000);
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#endif
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
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/* Page address translation */
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vsid = sr & 0x00FFFFFF;
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pgidx = (virtual >> 12) & 0xFFFF;
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sdr = env->sdr1;
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hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
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mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
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pg_addr = get_pgaddr(sdr, hash, mask);
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ptem = (vsid << 7) | (pgidx >> 10);
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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"hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
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pg_addr);
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}
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#endif
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/* Primary table lookup */
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ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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if (ret < 0) {
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/* Secondary table lookup */
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hash = (~hash) & 0x01FFFFC0;
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pg_addr = get_pgaddr(sdr, hash, mask);
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#if defined (DEBUG_MMU)
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if (virtual != 0xEFFFFFFF && loglevel > 0) {
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fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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"hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
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hash, pg_addr);
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}
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#endif
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ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
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if (ret2 != -1)
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ret = ret2;
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}
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} else {
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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fprintf(logfile, "No access allowed\n");
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#endif
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ret = -3;
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}
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} else {
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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fprintf(logfile, "direct store...\n");
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#endif
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/* Direct-store segment : absolutely *BUGGY* for now */
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switch (type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_CODE:
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/* No code fetch is allowed in direct-store areas */
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return -4;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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return -4;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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return -4;
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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*real = virtual;
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return 0;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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return -4;
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default:
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if (logfile) {
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fprintf(logfile, "ERROR: instruction should not need "
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"address translation\n");
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}
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printf("ERROR: instruction should not need "
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"address translation\n");
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return -4;
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}
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if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
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*real = virtual;
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ret = 2;
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} else {
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ret = -2;
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}
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}
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return ret;
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}
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int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
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uint32_t address, int rw, int access_type)
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{
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int ret;
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#if 0
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if (loglevel > 0) {
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fprintf(logfile, "%s\n", __func__);
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}
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#endif
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if ((access_type == ACCESS_CODE && msr_ir == 0) ||
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(access_type != ACCESS_CODE && msr_dr == 0)) {
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/* No address translation */
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*physical = address & ~0xFFF;
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*prot = PAGE_READ | PAGE_WRITE;
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ret = 0;
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} else {
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/* Try to find a BAT */
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ret = get_bat(env, physical, prot, address, rw, access_type);
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if (ret < 0) {
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/* We didn't match any BAT entry */
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ret = get_segment(env, physical, prot, address, rw, access_type);
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}
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}
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#if 0
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if (loglevel > 0) {
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fprintf(logfile, "%s address %08x => %08x\n",
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__func__, address, *physical);
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}
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#endif
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return ret;
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}
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#if defined(CONFIG_USER_ONLY)
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target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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return addr;
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}
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#else
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target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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uint32_t phys_addr;
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int prot;
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
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return -1;
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return phys_addr;
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define GETPC() (__builtin_return_address(0))
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|
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
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{
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TranslationBlock *tb;
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CPUState *saved_env;
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unsigned long pc;
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int ret;
|
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|
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env;
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env = cpu_single_env;
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#if 0
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{
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unsigned long tlb_addrr, tlb_addrw;
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int index;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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tlb_addrr = env->tlb_read[is_user][index].address;
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tlb_addrw = env->tlb_write[is_user][index].address;
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if (loglevel) {
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fprintf(logfile,
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"%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
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"(0x%08lx 0x%08lx)\n", __func__, env,
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&env->tlb_read[is_user][index], index, addr,
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tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
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tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
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}
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}
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#endif
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ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
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if (ret) {
|
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if (retaddr) {
|
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/* now we have a real cpu fault */
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pc = (unsigned long)retaddr;
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, NULL);
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}
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}
|
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do_raise_exception_err(env->exception_index, env->error_code);
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}
|
|
#if 0
|
|
{
|
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unsigned long tlb_addrr, tlb_addrw;
|
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int index;
|
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
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tlb_addrr = env->tlb_read[is_user][index].address;
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tlb_addrw = env->tlb_write[is_user][index].address;
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printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
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"(0x%08lx 0x%08lx)\n", __func__, env,
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&env->tlb_read[is_user][index], index, addr,
|
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tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
|
tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
|
}
|
|
#endif
|
|
env = saved_env;
|
|
}
|
|
|
|
void cpu_ppc_init_mmu(CPUState *env)
|
|
{
|
|
/* Nothing to do: all translation are disabled */
|
|
}
|
|
#endif
|
|
|
|
/* Perform address translation */
|
|
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
|
|
int is_user, int is_softmmu)
|
|
{
|
|
uint32_t physical;
|
|
int prot;
|
|
int exception = 0, error_code = 0;
|
|
int access_type;
|
|
int ret = 0;
|
|
|
|
if (rw == 2) {
|
|
/* code access */
|
|
rw = 0;
|
|
access_type = ACCESS_CODE;
|
|
} else {
|
|
/* data access */
|
|
/* XXX: put correct access by using cpu_restore_state()
|
|
correctly */
|
|
access_type = ACCESS_INT;
|
|
// access_type = env->access_type;
|
|
}
|
|
if (env->user_mode_only) {
|
|
/* user mode only emulation */
|
|
ret = -2;
|
|
goto do_fault;
|
|
}
|
|
ret = get_physical_address(env, &physical, &prot,
|
|
address, rw, access_type);
|
|
if (ret == 0) {
|
|
ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
|
|
is_user, is_softmmu);
|
|
} else if (ret < 0) {
|
|
do_fault:
|
|
#if defined (DEBUG_MMU)
|
|
if (loglevel > 0)
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
|
#endif
|
|
if (access_type == ACCESS_CODE) {
|
|
exception = EXCP_ISI;
|
|
switch (ret) {
|
|
case -1:
|
|
/* No matches in page tables */
|
|
error_code = EXCP_ISI_TRANSLATE;
|
|
break;
|
|
case -2:
|
|
/* Access rights violation */
|
|
error_code = EXCP_ISI_PROT;
|
|
break;
|
|
case -3:
|
|
/* No execute protection violation */
|
|
error_code = EXCP_ISI_NOEXEC;
|
|
break;
|
|
case -4:
|
|
/* Direct store exception */
|
|
/* No code fetch is allowed in direct-store areas */
|
|
error_code = EXCP_ISI_DIRECT;
|
|
break;
|
|
}
|
|
} else {
|
|
exception = EXCP_DSI;
|
|
switch (ret) {
|
|
case -1:
|
|
/* No matches in page tables */
|
|
error_code = EXCP_DSI_TRANSLATE;
|
|
break;
|
|
case -2:
|
|
/* Access rights violation */
|
|
error_code = EXCP_DSI_PROT;
|
|
break;
|
|
case -4:
|
|
/* Direct store exception */
|
|
switch (access_type) {
|
|
case ACCESS_FLOAT:
|
|
/* Floating point load/store */
|
|
exception = EXCP_ALIGN;
|
|
error_code = EXCP_ALIGN_FP;
|
|
break;
|
|
case ACCESS_RES:
|
|
/* lwarx, ldarx or srwcx. */
|
|
exception = EXCP_DSI;
|
|
error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
|
|
break;
|
|
case ACCESS_EXT:
|
|
/* eciwx or ecowx */
|
|
exception = EXCP_DSI;
|
|
error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
|
|
EXCP_DSI_ECXW;
|
|
break;
|
|
default:
|
|
printf("DSI: invalid exception (%d)\n", ret);
|
|
exception = EXCP_PROGRAM;
|
|
error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
|
|
break;
|
|
}
|
|
}
|
|
if (rw)
|
|
error_code |= EXCP_DSI_STORE;
|
|
/* Store fault address */
|
|
env->spr[DAR] = address;
|
|
}
|
|
#if 0
|
|
printf("%s: set exception to %d %02x\n",
|
|
__func__, exception, error_code);
|
|
#endif
|
|
env->exception_index = exception;
|
|
env->error_code = error_code;
|
|
ret = 1;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
uint32_t _load_xer (CPUState *env)
|
|
{
|
|
return (xer_so << XER_SO) |
|
|
(xer_ov << XER_OV) |
|
|
(xer_ca << XER_CA) |
|
|
(xer_bc << XER_BC);
|
|
}
|
|
|
|
void _store_xer (CPUState *env, uint32_t value)
|
|
{
|
|
xer_so = (value >> XER_SO) & 0x01;
|
|
xer_ov = (value >> XER_OV) & 0x01;
|
|
xer_ca = (value >> XER_CA) & 0x01;
|
|
xer_bc = (value >> XER_BC) & 0x1f;
|
|
}
|
|
|
|
uint32_t _load_msr (CPUState *env)
|
|
{
|
|
return (msr_pow << MSR_POW) |
|
|
(msr_ile << MSR_ILE) |
|
|
(msr_ee << MSR_EE) |
|
|
(msr_pr << MSR_PR) |
|
|
(msr_fp << MSR_FP) |
|
|
(msr_me << MSR_ME) |
|
|
(msr_fe0 << MSR_FE0) |
|
|
(msr_se << MSR_SE) |
|
|
(msr_be << MSR_BE) |
|
|
(msr_fe1 << MSR_FE1) |
|
|
(msr_ip << MSR_IP) |
|
|
(msr_ir << MSR_IR) |
|
|
(msr_dr << MSR_DR) |
|
|
(msr_ri << MSR_RI) |
|
|
(msr_le << MSR_LE);
|
|
}
|
|
|
|
void _store_msr (CPUState *env, uint32_t value)
|
|
{
|
|
#if 0 // TRY
|
|
if (((value >> MSR_IR) & 0x01) != msr_ir ||
|
|
((value >> MSR_DR) & 0x01) != msr_dr)
|
|
{
|
|
/* Flush all tlb when changing translation mode or privilege level */
|
|
tlb_flush(env, 1);
|
|
}
|
|
#endif
|
|
msr_pow = (value >> MSR_POW) & 0x03;
|
|
msr_ile = (value >> MSR_ILE) & 0x01;
|
|
msr_ee = (value >> MSR_EE) & 0x01;
|
|
msr_pr = (value >> MSR_PR) & 0x01;
|
|
msr_fp = (value >> MSR_FP) & 0x01;
|
|
msr_me = (value >> MSR_ME) & 0x01;
|
|
msr_fe0 = (value >> MSR_FE0) & 0x01;
|
|
msr_se = (value >> MSR_SE) & 0x01;
|
|
msr_be = (value >> MSR_BE) & 0x01;
|
|
msr_fe1 = (value >> MSR_FE1) & 0x01;
|
|
msr_ip = (value >> MSR_IP) & 0x01;
|
|
msr_ir = (value >> MSR_IR) & 0x01;
|
|
msr_dr = (value >> MSR_DR) & 0x01;
|
|
msr_ri = (value >> MSR_RI) & 0x01;
|
|
msr_le = (value >> MSR_LE) & 0x01;
|
|
}
|
|
|
|
void do_interrupt (CPUState *env)
|
|
{
|
|
#if defined (CONFIG_USER_ONLY)
|
|
env->exception_index |= 0x100;
|
|
#else
|
|
uint32_t msr;
|
|
int excp = env->exception_index;
|
|
|
|
msr = _load_msr(env);
|
|
#if defined (DEBUG_EXCEPTIONS)
|
|
if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
|
|
{
|
|
if (loglevel > 0) {
|
|
fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
|
env->nip, excp << 8, env->error_code);
|
|
}
|
|
if (loglevel > 0)
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
|
}
|
|
#endif
|
|
if (loglevel & CPU_LOG_INT) {
|
|
fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
|
env->nip, excp << 8, env->error_code);
|
|
}
|
|
/* Generate informations in save/restore registers */
|
|
switch (excp) {
|
|
case EXCP_OFCALL:
|
|
#if defined (USE_OPEN_FIRMWARE)
|
|
env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
|
|
#endif
|
|
return;
|
|
case EXCP_RTASCALL:
|
|
#if defined (USE_OPEN_FIRMWARE)
|
|
printf("RTAS call !\n");
|
|
env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
|
|
printf("RTAS call done\n");
|
|
#endif
|
|
return;
|
|
case EXCP_NONE:
|
|
/* Do nothing */
|
|
#if defined (DEBUG_EXCEPTIONS)
|
|
printf("%s: escape EXCP_NONE\n", __func__);
|
|
#endif
|
|
return;
|
|
case EXCP_RESET:
|
|
if (msr_ip)
|
|
excp += 0xFFC00;
|
|
goto store_next;
|
|
case EXCP_MACHINE_CHECK:
|
|
if (msr_me == 0) {
|
|
cpu_abort(env, "Machine check exception while not allowed\n");
|
|
}
|
|
msr_me = 0;
|
|
break;
|
|
case EXCP_DSI:
|
|
/* Store exception cause */
|
|
/* data location address has been stored
|
|
* when the fault has been detected
|
|
*/
|
|
msr &= ~0xFFFF0000;
|
|
env->spr[DSISR] = 0;
|
|
if (env->error_code & EXCP_DSI_TRANSLATE)
|
|
env->spr[DSISR] |= 0x40000000;
|
|
else if (env->error_code & EXCP_DSI_PROT)
|
|
env->spr[DSISR] |= 0x08000000;
|
|
else if (env->error_code & EXCP_DSI_NOTSUP) {
|
|
env->spr[DSISR] |= 0x80000000;
|
|
if (env->error_code & EXCP_DSI_DIRECT)
|
|
env->spr[DSISR] |= 0x04000000;
|
|
}
|
|
if (env->error_code & EXCP_DSI_STORE)
|
|
env->spr[DSISR] |= 0x02000000;
|
|
if ((env->error_code & 0xF) == EXCP_DSI_DABR)
|
|
env->spr[DSISR] |= 0x00400000;
|
|
if (env->error_code & EXCP_DSI_ECXW)
|
|
env->spr[DSISR] |= 0x00100000;
|
|
#if defined (DEBUG_EXCEPTIONS)
|
|
if (loglevel) {
|
|
fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
|
|
env->spr[DSISR], env->spr[DAR]);
|
|
} else {
|
|
printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
|
|
env->spr[DSISR], env->spr[DAR], env->nip);
|
|
}
|
|
#endif
|
|
goto store_next;
|
|
case EXCP_ISI:
|
|
/* Store exception cause */
|
|
msr &= ~0xFFFF0000;
|
|
if (env->error_code == EXCP_ISI_TRANSLATE)
|
|
msr |= 0x40000000;
|
|
else if (env->error_code == EXCP_ISI_NOEXEC ||
|
|
env->error_code == EXCP_ISI_GUARD ||
|
|
env->error_code == EXCP_ISI_DIRECT)
|
|
msr |= 0x10000000;
|
|
else
|
|
msr |= 0x08000000;
|
|
#if defined (DEBUG_EXCEPTIONS)
|
|
if (loglevel) {
|
|
fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
|
|
msr, env->nip);
|
|
} else {
|
|
printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
|
|
msr, env->nip, env->spr[V_TBL]);
|
|
}
|
|
#endif
|
|
goto store_next;
|
|
case EXCP_EXTERNAL:
|
|
if (msr_ee == 0) {
|
|
#if defined (DEBUG_EXCEPTIONS)
|
|
if (loglevel > 0) {
|
|
fprintf(logfile, "Skipping hardware interrupt\n");
|
|
}
|
|
#endif
|
|
/* Requeue it */
|
|
do_raise_exception(EXCP_EXTERNAL);
|
|
return;
|
|
}
|
|
goto store_next;
|
|
case EXCP_ALIGN:
|
|
/* Store exception cause */
|
|
/* Get rS/rD and rA from faulting opcode */
|
|
env->spr[DSISR] |=
|
|
(ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
|
|
/* data location address has been stored
|
|
* when the fault has been detected
|
|
*/
|
|
goto store_current;
|
|
case EXCP_PROGRAM:
|
|
msr &= ~0xFFFF0000;
|
|
switch (env->error_code & ~0xF) {
|
|
case EXCP_FP:
|
|
if (msr_fe0 == 0 && msr_fe1 == 0) {
|
|
#if defined (DEBUG_EXCEPTIONS)
|
|
printf("Ignore floating point exception\n");
|
|
#endif
|
|
return;
|
|
}
|
|
msr |= 0x00100000;
|
|
/* Set FX */
|
|
env->fpscr[7] |= 0x8;
|
|
/* Finally, update FEX */
|
|
if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
|
|
((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
|
|
env->fpscr[7] |= 0x4;
|
|
break;
|
|
case EXCP_INVAL:
|
|
// printf("Invalid instruction at 0x%08x\n", env->nip);
|
|
msr |= 0x00080000;
|
|
break;
|
|
case EXCP_PRIV:
|
|
msr |= 0x00040000;
|
|
break;
|
|
case EXCP_TRAP:
|
|
msr |= 0x00020000;
|
|
break;
|
|
default:
|
|
/* Should never occur */
|
|
break;
|
|
}
|
|
msr |= 0x00010000;
|
|
goto store_current;
|
|
case EXCP_NO_FP:
|
|
goto store_current;
|
|
case EXCP_DECR:
|
|
if (msr_ee == 0) {
|
|
/* Requeue it */
|
|
do_raise_exception(EXCP_DECR);
|
|
return;
|
|
}
|
|
goto store_next;
|
|
case EXCP_SYSCALL:
|
|
if (loglevel & CPU_LOG_INT) {
|
|
fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
env->gpr[0], env->gpr[3], env->gpr[4],
|
|
env->gpr[5], env->gpr[6]);
|
|
if (env->gpr[0] == 4 && env->gpr[3] == 1) {
|
|
int len, addr, i;
|
|
uint8_t c;
|
|
|
|
fprintf(logfile, "write: ");
|
|
addr = env->gpr[4];
|
|
len = env->gpr[5];
|
|
if (len > 64)
|
|
len = 64;
|
|
for(i = 0; i < len; i++) {
|
|
c = 0;
|
|
cpu_memory_rw_debug(env, addr + i, &c, 1, 0);
|
|
if (c < 32 || c > 126)
|
|
c = '.';
|
|
fprintf(logfile, "%c", c);
|
|
}
|
|
fprintf(logfile, "\n");
|
|
}
|
|
}
|
|
goto store_next;
|
|
case EXCP_TRACE:
|
|
goto store_next;
|
|
case EXCP_FP_ASSIST:
|
|
goto store_next;
|
|
case EXCP_MTMSR:
|
|
/* Nothing to do */
|
|
return;
|
|
case EXCP_BRANCH:
|
|
/* Nothing to do */
|
|
return;
|
|
case EXCP_RFI:
|
|
/* Restore user-mode state */
|
|
tb_flush(env);
|
|
#if defined (DEBUG_EXCEPTIONS)
|
|
if (msr_pr == 1)
|
|
printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
|
|
#endif
|
|
return;
|
|
store_current:
|
|
/* SRR0 is set to current instruction */
|
|
env->spr[SRR0] = (uint32_t)env->nip - 4;
|
|
break;
|
|
store_next:
|
|
/* SRR0 is set to next instruction */
|
|
env->spr[SRR0] = (uint32_t)env->nip;
|
|
break;
|
|
}
|
|
env->spr[SRR1] = msr;
|
|
/* reload MSR with correct bits */
|
|
msr_pow = 0;
|
|
msr_ee = 0;
|
|
msr_pr = 0;
|
|
msr_fp = 0;
|
|
msr_fe0 = 0;
|
|
msr_se = 0;
|
|
msr_be = 0;
|
|
msr_fe1 = 0;
|
|
msr_ir = 0;
|
|
msr_dr = 0;
|
|
msr_ri = 0;
|
|
msr_le = msr_ile;
|
|
/* Jump to handler */
|
|
env->nip = excp << 8;
|
|
env->exception_index = EXCP_NONE;
|
|
/* Invalidate all TLB as we may have changed translation mode */
|
|
tlb_flush(env, 1);
|
|
/* ensure that no TB jump will be modified as
|
|
the program flow was changed */
|
|
#ifdef __sparc__
|
|
tmp_T0 = 0;
|
|
#else
|
|
T0 = 0;
|
|
#endif
|
|
#endif
|
|
env->exception_index = -1;
|
|
}
|