e4ea952fb0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-41-richard.henderson@linaro.org>
348 lines
9.0 KiB
C
348 lines
9.0 KiB
C
/*
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* IMX31 Clock Control Module
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*
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* Copyright (C) 2012 NICTA
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* To get the timer frequencies right, we need to emulate at least part of
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* the i.MX31 CCM.
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/imx31_ccm.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define CKIH_FREQ 26000000 /* 26MHz crystal input */
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#ifndef DEBUG_IMX31_CCM
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#define DEBUG_IMX31_CCM 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX31_CCM) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
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__func__, ##args); \
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} \
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} while (0)
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static const char *imx31_ccm_reg_name(uint32_t reg)
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{
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static char unknown[20];
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switch (reg) {
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case IMX31_CCM_CCMR_REG:
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return "CCMR";
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case IMX31_CCM_PDR0_REG:
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return "PDR0";
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case IMX31_CCM_PDR1_REG:
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return "PDR1";
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case IMX31_CCM_RCSR_REG:
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return "RCSR";
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case IMX31_CCM_MPCTL_REG:
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return "MPCTL";
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case IMX31_CCM_UPCTL_REG:
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return "UPCTL";
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case IMX31_CCM_SPCTL_REG:
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return "SPCTL";
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case IMX31_CCM_COSR_REG:
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return "COSR";
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case IMX31_CCM_CGR0_REG:
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return "CGR0";
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case IMX31_CCM_CGR1_REG:
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return "CGR1";
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case IMX31_CCM_CGR2_REG:
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return "CGR2";
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case IMX31_CCM_WIMR_REG:
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return "WIMR";
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case IMX31_CCM_LDC_REG:
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return "LDC";
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case IMX31_CCM_DCVR0_REG:
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return "DCVR0";
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case IMX31_CCM_DCVR1_REG:
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return "DCVR1";
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case IMX31_CCM_DCVR2_REG:
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return "DCVR2";
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case IMX31_CCM_DCVR3_REG:
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return "DCVR3";
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case IMX31_CCM_LTR0_REG:
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return "LTR0";
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case IMX31_CCM_LTR1_REG:
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return "LTR1";
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case IMX31_CCM_LTR2_REG:
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return "LTR2";
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case IMX31_CCM_LTR3_REG:
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return "LTR3";
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case IMX31_CCM_LTBR0_REG:
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return "LTBR0";
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case IMX31_CCM_LTBR1_REG:
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return "LTBR1";
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case IMX31_CCM_PMCR0_REG:
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return "PMCR0";
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case IMX31_CCM_PMCR1_REG:
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return "PMCR1";
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case IMX31_CCM_PDR2_REG:
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return "PDR2";
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default:
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sprintf(unknown, "[%u ?]", reg);
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return unknown;
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}
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}
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static const VMStateDescription vmstate_imx31_ccm = {
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.name = TYPE_IMX31_CCM,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
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VMSTATE_END_OF_LIST()
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},
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};
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static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
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{
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uint32_t freq = 0;
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IMX31CCMState *s = IMX31_CCM(dev);
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if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
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if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
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freq = CKIL_FREQ;
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if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
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freq *= 1024;
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}
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}
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} else {
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freq = CKIH_FREQ;
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}
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DPRINTF("freq = %u\n", freq);
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return freq;
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}
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static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
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imx31_ccm_get_pll_ref_clk(dev));
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DPRINTF("freq = %u\n", freq);
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return freq;
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}
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static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
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!(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
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freq = imx31_ccm_get_pll_ref_clk(dev);
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} else {
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freq = imx31_ccm_get_mpll_clk(dev);
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}
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DPRINTF("freq = %u\n", freq);
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return freq;
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}
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static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx31_ccm_get_mcu_main_clk(dev)
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/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
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DPRINTF("freq = %u\n", freq);
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return freq;
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}
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static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx31_ccm_get_hclk_clk(dev)
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/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
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DPRINTF("freq = %u\n", freq);
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return freq;
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}
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static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
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{
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uint32_t freq = 0;
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switch (clock) {
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case CLK_NONE:
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break;
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case CLK_IPG:
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case CLK_IPG_HIGH:
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freq = imx31_ccm_get_ipg_clk(dev);
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break;
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case CLK_32k:
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freq = CKIL_FREQ;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
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TYPE_IMX31_CCM, __func__, clock);
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break;
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}
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DPRINTF("Clock = %d) = %u\n", clock, freq);
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return freq;
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}
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static void imx31_ccm_reset(DeviceState *dev)
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{
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IMX31CCMState *s = IMX31_CCM(dev);
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DPRINTF("()\n");
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memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
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s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d;
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s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48;
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s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f;
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s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000;
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s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800;
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s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03;
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s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001;
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s->reg[IMX31_CCM_COSR_REG] = 0x00000280;
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s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff;
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s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff;
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s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff;
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s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff;
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s->reg[IMX31_CCM_LTR1_REG] = 0x00004040;
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s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828;
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s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000;
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s->reg[IMX31_CCM_PDR2_REG] = 0x00000285;
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}
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static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t value = 0;
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IMX31CCMState *s = (IMX31CCMState *)opaque;
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if ((offset >> 2) < IMX31_CCM_MAX_REG) {
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value = s->reg[offset >> 2];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
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}
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DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
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value);
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return (uint64_t)value;
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}
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static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMX31CCMState *s = (IMX31CCMState *)opaque;
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DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
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(uint32_t)value);
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switch (offset >> 2) {
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case IMX31_CCM_CCMR_REG:
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s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
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break;
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case IMX31_CCM_PDR0_REG:
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s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
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break;
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case IMX31_CCM_PDR1_REG:
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s->reg[IMX31_CCM_PDR1_REG] = value;
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break;
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case IMX31_CCM_MPCTL_REG:
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s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
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break;
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case IMX31_CCM_SPCTL_REG:
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s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
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break;
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case IMX31_CCM_CGR0_REG:
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s->reg[IMX31_CCM_CGR0_REG] = value;
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break;
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case IMX31_CCM_CGR1_REG:
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s->reg[IMX31_CCM_CGR1_REG] = value;
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break;
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case IMX31_CCM_CGR2_REG:
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s->reg[IMX31_CCM_CGR2_REG] = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
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break;
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}
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}
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static const struct MemoryRegionOps imx31_ccm_ops = {
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.read = imx31_ccm_read,
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.write = imx31_ccm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx31_ccm_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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SysBusDevice *sd = SYS_BUS_DEVICE(obj);
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IMX31CCMState *s = IMX31_CCM(obj);
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memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
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TYPE_IMX31_CCM, 0x1000);
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sysbus_init_mmio(sd, &s->iomem);
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}
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static void imx31_ccm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
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dc->reset = imx31_ccm_reset;
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dc->vmsd = &vmstate_imx31_ccm;
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dc->desc = "i.MX31 Clock Control Module";
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ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
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}
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static const TypeInfo imx31_ccm_info = {
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.name = TYPE_IMX31_CCM,
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.parent = TYPE_IMX_CCM,
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.instance_size = sizeof(IMX31CCMState),
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.instance_init = imx31_ccm_init,
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.class_init = imx31_ccm_class_init,
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};
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static void imx31_ccm_register_types(void)
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{
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type_register_static(&imx31_ccm_info);
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}
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type_init(imx31_ccm_register_types)
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