54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch ipi interrupt header files
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef HW_LOONGARCH_IPI_H
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#define HW_LOONGARCH_IPI_H
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#include "hw/sysbus.h"
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/* Mainy used by iocsr read and write */
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#define SMP_IPI_MAILBOX 0x1000ULL
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#define CORE_STATUS_OFF 0x0
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#define CORE_EN_OFF 0x4
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#define CORE_SET_OFF 0x8
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#define CORE_CLEAR_OFF 0xc
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#define CORE_BUF_20 0x20
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#define CORE_BUF_28 0x28
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#define CORE_BUF_30 0x30
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#define CORE_BUF_38 0x38
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#define IOCSR_IPI_SEND 0x40
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#define IOCSR_MAIL_SEND 0x48
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#define IOCSR_ANY_SEND 0x158
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#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
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#define MAIL_SEND_OFFSET 0
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#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
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#define MAX_IPI_CORE_NUM 4
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#define MAX_IPI_MBX_NUM 4
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#define TYPE_LOONGARCH_IPI "loongarch_ipi"
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OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
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typedef struct IPICore {
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uint32_t status;
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uint32_t en;
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uint32_t set;
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uint32_t clear;
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/* 64bit buf divide into 2 32bit buf */
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uint32_t buf[MAX_IPI_MBX_NUM * 2];
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qemu_irq irq;
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} IPICore;
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struct LoongArchIPI {
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SysBusDevice parent_obj;
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MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM];
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MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM];
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};
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#endif
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