46aa848ffb
Add instructions of SSR opcode format. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-9-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
732 lines
21 KiB
C
732 lines
21 KiB
C
/*
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* TriCore emulation for qemu: main translation routines.
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*
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* Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "disas/disas.h"
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#include "tcg-op.h"
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "tricore-opcodes.h"
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/*
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* TCG registers
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*/
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static TCGv cpu_PC;
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static TCGv cpu_PCXI;
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static TCGv cpu_PSW;
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static TCGv cpu_ICR;
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/* GPR registers */
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static TCGv cpu_gpr_a[16];
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static TCGv cpu_gpr_d[16];
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/* PSW Flag cache */
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static TCGv cpu_PSW_C;
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static TCGv cpu_PSW_V;
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static TCGv cpu_PSW_SV;
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static TCGv cpu_PSW_AV;
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static TCGv cpu_PSW_SAV;
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/* CPU env */
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static TCGv_ptr cpu_env;
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#include "exec/gen-icount.h"
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static const char *regnames_a[] = {
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"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
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"a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
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"a12" , "a13" , "a14" , "a15",
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};
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static const char *regnames_d[] = {
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"d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
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"d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
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"d12" , "d13" , "d14" , "d15",
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};
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typedef struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong pc, saved_pc, next_pc;
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uint32_t opcode;
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int singlestep_enabled;
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/* Routine used to access memory */
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int mem_idx;
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uint32_t hflags, saved_hflags;
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int bstate;
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} DisasContext;
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enum {
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BS_NONE = 0,
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BS_STOP = 1,
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BS_BRANCH = 2,
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BS_EXCP = 3,
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};
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void tricore_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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int i;
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cpu_fprintf(f, "PC=%08x\n", env->PC);
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for (i = 0; i < 16; ++i) {
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if ((i & 3) == 0) {
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cpu_fprintf(f, "GPR A%02d:", i);
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}
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cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
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}
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for (i = 0; i < 16; ++i) {
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if ((i & 3) == 0) {
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cpu_fprintf(f, "GPR D%02d:", i);
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}
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cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
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}
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}
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/*
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* Functions to generate micro-ops
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*/
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/* Functions for arithmetic instructions */
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static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
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{
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TCGv t0 = tcg_temp_new_i32();
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TCGv result = tcg_temp_new_i32();
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/* Addition and set V/SV bits */
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tcg_gen_add_tl(result, r1, r2);
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/* calc V bit */
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tcg_gen_xor_tl(cpu_PSW_V, result, r1);
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tcg_gen_xor_tl(t0, r1, r2);
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tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
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/* Calc SV bit */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* Calc AV/SAV bits */
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tcg_gen_add_tl(cpu_PSW_AV, result, result);
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tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
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/* calc SAV */
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tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
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/* write back result */
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tcg_gen_mov_tl(ret, result);
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tcg_temp_free(result);
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tcg_temp_free(t0);
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}
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static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
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{
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TCGv temp = tcg_const_i32(r2);
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gen_add_d(ret, r1, temp);
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tcg_temp_free(temp);
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}
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static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
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TCGv r4)
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{
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TCGv temp = tcg_temp_new();
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TCGv temp2 = tcg_temp_new();
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TCGv result = tcg_temp_new();
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TCGv mask = tcg_temp_new();
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TCGv t0 = tcg_const_i32(0);
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/* create mask for sticky bits */
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tcg_gen_setcond_tl(cond, mask, r4, t0);
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tcg_gen_shli_tl(mask, mask, 31);
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tcg_gen_add_tl(result, r1, r2);
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/* Calc PSW_V */
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tcg_gen_xor_tl(temp, result, r1);
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tcg_gen_xor_tl(temp2, r1, r2);
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tcg_gen_andc_tl(temp, temp, temp2);
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tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
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/* Set PSW_SV */
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tcg_gen_and_tl(temp, temp, mask);
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tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
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/* calc AV bit */
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tcg_gen_add_tl(temp, result, result);
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tcg_gen_xor_tl(temp, temp, result);
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tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
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/* calc SAV bit */
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tcg_gen_and_tl(temp, temp, mask);
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tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
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/* write back result */
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tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
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tcg_temp_free(t0);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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tcg_temp_free(result);
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tcg_temp_free(mask);
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}
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static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
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TCGv r3, TCGv r4)
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{
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TCGv temp = tcg_const_i32(r2);
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gen_cond_add(cond, r1, temp, r3, r4);
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tcg_temp_free(temp);
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}
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static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
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{
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TCGv temp = tcg_temp_new_i32();
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TCGv result = tcg_temp_new_i32();
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tcg_gen_sub_tl(result, r1, r2);
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/* calc V bit */
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tcg_gen_xor_tl(cpu_PSW_V, result, r1);
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tcg_gen_xor_tl(temp, r1, r2);
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tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
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/* calc SV bit */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* Calc AV bit */
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tcg_gen_add_tl(cpu_PSW_AV, result, result);
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tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
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/* calc SAV bit */
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tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
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/* write back result */
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tcg_gen_mov_tl(ret, result);
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tcg_temp_free(temp);
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tcg_temp_free(result);
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}
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static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
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{
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TCGv high = tcg_temp_new();
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TCGv low = tcg_temp_new();
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tcg_gen_muls2_tl(low, high, r1, r2);
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tcg_gen_mov_tl(ret, low);
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/* calc V bit */
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tcg_gen_sari_tl(low, low, 31);
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tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
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tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
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/* calc SV bit */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* Calc AV bit */
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tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
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tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
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/* calc SAV bit */
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tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
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tcg_temp_free(high);
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tcg_temp_free(low);
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}
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static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
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{
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if (shift_count == -32) {
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tcg_gen_movi_tl(ret, 0);
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} else if (shift_count >= 0) {
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tcg_gen_shli_tl(ret, r1, shift_count);
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} else {
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tcg_gen_shri_tl(ret, r1, -shift_count);
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}
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}
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static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
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{
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uint32_t msk, msk_start;
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TCGv temp = tcg_temp_new();
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TCGv temp2 = tcg_temp_new();
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TCGv t_0 = tcg_const_i32(0);
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if (shift_count == 0) {
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/* Clear PSW.C and PSW.V */
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tcg_gen_movi_tl(cpu_PSW_C, 0);
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tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
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tcg_gen_mov_tl(ret, r1);
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} else if (shift_count == -32) {
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/* set PSW.C */
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tcg_gen_mov_tl(cpu_PSW_C, r1);
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/* fill ret completly with sign bit */
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tcg_gen_sari_tl(ret, r1, 31);
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/* clear PSW.V */
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tcg_gen_movi_tl(cpu_PSW_V, 0);
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} else if (shift_count > 0) {
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TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
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TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
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/* calc carry */
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msk_start = 32 - shift_count;
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msk = ((1 << shift_count) - 1) << msk_start;
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tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
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/* calc v/sv bits */
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tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
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tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
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tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
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tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
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/* calc sv */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
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/* do shift */
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tcg_gen_shli_tl(ret, r1, shift_count);
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tcg_temp_free(t_max);
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tcg_temp_free(t_min);
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} else {
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/* clear PSW.V */
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tcg_gen_movi_tl(cpu_PSW_V, 0);
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/* calc carry */
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msk = (1 << -shift_count) - 1;
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tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
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/* do shift */
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tcg_gen_sari_tl(ret, r1, -shift_count);
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}
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/* calc av overflow bit */
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tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
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tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
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/* calc sav overflow bit */
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tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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tcg_temp_free(t_0);
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}
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static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
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{
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gen_helper_add_ssov(ret, cpu_env, r1, r2);
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}
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static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
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{
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gen_helper_sub_ssov(ret, cpu_env, r1, r2);
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}
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/*
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* Functions for decoding instructions
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*/
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static void decode_src_opc(DisasContext *ctx, int op1)
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{
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int r1;
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int32_t const4;
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TCGv temp, temp2;
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r1 = MASK_OP_SRC_S1D(ctx->opcode);
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const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
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switch (op1) {
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case OPC1_16_SRC_ADD:
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gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_ADD_A15:
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gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
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break;
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case OPC1_16_SRC_ADD_15A:
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gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_ADD_A:
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tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
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break;
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case OPC1_16_SRC_CADD:
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gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
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cpu_gpr_d[15]);
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break;
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case OPC1_16_SRC_CADDN:
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gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
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cpu_gpr_d[15]);
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break;
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case OPC1_16_SRC_CMOV:
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temp = tcg_const_tl(0);
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temp2 = tcg_const_tl(const4);
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tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
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temp2, cpu_gpr_d[r1]);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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case OPC1_16_SRC_CMOVN:
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temp = tcg_const_tl(0);
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temp2 = tcg_const_tl(const4);
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tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
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temp2, cpu_gpr_d[r1]);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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case OPC1_16_SRC_EQ:
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tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
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const4);
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break;
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case OPC1_16_SRC_LT:
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tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
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const4);
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break;
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case OPC1_16_SRC_MOV:
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tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_MOV_A:
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const4 = MASK_OP_SRC_CONST4(ctx->opcode);
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tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
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break;
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case OPC1_16_SRC_SH:
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gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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break;
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case OPC1_16_SRC_SHA:
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gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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break;
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}
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}
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static void decode_srr_opc(DisasContext *ctx, int op1)
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{
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int r1, r2;
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TCGv temp;
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r1 = MASK_OP_SRR_S1D(ctx->opcode);
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r2 = MASK_OP_SRR_S2(ctx->opcode);
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switch (op1) {
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case OPC1_16_SRR_ADD:
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gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
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break;
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case OPC1_16_SRR_ADD_A15:
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gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
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break;
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case OPC1_16_SRR_ADD_15A:
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gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
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break;
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case OPC1_16_SRR_ADD_A:
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tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
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break;
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case OPC1_16_SRR_ADDS:
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gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
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break;
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case OPC1_16_SRR_AND:
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tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
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break;
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case OPC1_16_SRR_CMOV:
|
|
temp = tcg_const_tl(0);
|
|
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
|
|
cpu_gpr_d[r2], cpu_gpr_d[r1]);
|
|
tcg_temp_free(temp);
|
|
break;
|
|
case OPC1_16_SRR_CMOVN:
|
|
temp = tcg_const_tl(0);
|
|
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
|
|
cpu_gpr_d[r2], cpu_gpr_d[r1]);
|
|
tcg_temp_free(temp);
|
|
break;
|
|
case OPC1_16_SRR_EQ:
|
|
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
|
|
cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_LT:
|
|
tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
|
|
cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_MOV:
|
|
tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_MOV_A:
|
|
tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_MOV_AA:
|
|
tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
|
|
break;
|
|
case OPC1_16_SRR_MOV_D:
|
|
tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
|
|
break;
|
|
case OPC1_16_SRR_MUL:
|
|
gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_OR:
|
|
tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_SUB:
|
|
gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_SUB_A15B:
|
|
gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_SUB_15AB:
|
|
gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_SUBS:
|
|
gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
case OPC1_16_SRR_XOR:
|
|
tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void decode_ssr_opc(DisasContext *ctx, int op1)
|
|
{
|
|
int r1, r2;
|
|
|
|
r1 = MASK_OP_SSR_S1(ctx->opcode);
|
|
r2 = MASK_OP_SSR_S2(ctx->opcode);
|
|
|
|
switch (op1) {
|
|
case OPC1_16_SSR_ST_A:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
|
|
break;
|
|
case OPC1_16_SSR_ST_A_POSTINC:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
|
|
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
|
|
break;
|
|
case OPC1_16_SSR_ST_B:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
|
|
break;
|
|
case OPC1_16_SSR_ST_B_POSTINC:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
|
|
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
|
|
break;
|
|
case OPC1_16_SSR_ST_H:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
|
|
break;
|
|
case OPC1_16_SSR_ST_H_POSTINC:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
|
|
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
|
|
break;
|
|
case OPC1_16_SSR_ST_W:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
|
|
break;
|
|
case OPC1_16_SSR_ST_W_POSTINC:
|
|
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
|
|
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
|
|
{
|
|
int op1;
|
|
|
|
op1 = MASK_OP_MAJOR(ctx->opcode);
|
|
|
|
switch (op1) {
|
|
case OPC1_16_SRC_ADD:
|
|
case OPC1_16_SRC_ADD_A15:
|
|
case OPC1_16_SRC_ADD_15A:
|
|
case OPC1_16_SRC_ADD_A:
|
|
case OPC1_16_SRC_CADD:
|
|
case OPC1_16_SRC_CADDN:
|
|
case OPC1_16_SRC_CMOV:
|
|
case OPC1_16_SRC_CMOVN:
|
|
case OPC1_16_SRC_EQ:
|
|
case OPC1_16_SRC_LT:
|
|
case OPC1_16_SRC_MOV:
|
|
case OPC1_16_SRC_MOV_A:
|
|
case OPC1_16_SRC_SH:
|
|
case OPC1_16_SRC_SHA:
|
|
decode_src_opc(ctx, op1);
|
|
break;
|
|
/* SRR-format */
|
|
case OPC1_16_SRR_ADD:
|
|
case OPC1_16_SRR_ADD_A15:
|
|
case OPC1_16_SRR_ADD_15A:
|
|
case OPC1_16_SRR_ADD_A:
|
|
case OPC1_16_SRR_ADDS:
|
|
case OPC1_16_SRR_AND:
|
|
case OPC1_16_SRR_CMOV:
|
|
case OPC1_16_SRR_CMOVN:
|
|
case OPC1_16_SRR_EQ:
|
|
case OPC1_16_SRR_LT:
|
|
case OPC1_16_SRR_MOV:
|
|
case OPC1_16_SRR_MOV_A:
|
|
case OPC1_16_SRR_MOV_AA:
|
|
case OPC1_16_SRR_MOV_D:
|
|
case OPC1_16_SRR_MUL:
|
|
case OPC1_16_SRR_OR:
|
|
case OPC1_16_SRR_SUB:
|
|
case OPC1_16_SRR_SUB_A15B:
|
|
case OPC1_16_SRR_SUB_15AB:
|
|
case OPC1_16_SRR_SUBS:
|
|
case OPC1_16_SRR_XOR:
|
|
decode_srr_opc(ctx, op1);
|
|
break;
|
|
/* SSR-format */
|
|
case OPC1_16_SSR_ST_A:
|
|
case OPC1_16_SSR_ST_A_POSTINC:
|
|
case OPC1_16_SSR_ST_B:
|
|
case OPC1_16_SSR_ST_B_POSTINC:
|
|
case OPC1_16_SSR_ST_H:
|
|
case OPC1_16_SSR_ST_H_POSTINC:
|
|
case OPC1_16_SSR_ST_W:
|
|
case OPC1_16_SSR_ST_W_POSTINC:
|
|
decode_ssr_opc(ctx, op1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
|
|
{
|
|
}
|
|
|
|
static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
|
|
{
|
|
/* 16-Bit Instruction */
|
|
if ((ctx->opcode & 0x1) == 0) {
|
|
ctx->next_pc = ctx->pc + 2;
|
|
decode_16Bit_opc(env, ctx);
|
|
/* 32-Bit Instruction */
|
|
} else {
|
|
ctx->next_pc = ctx->pc + 4;
|
|
decode_32Bit_opc(env, ctx);
|
|
}
|
|
}
|
|
|
|
static inline void
|
|
gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
|
|
int search_pc)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUTriCoreState *env = &cpu->env;
|
|
DisasContext ctx;
|
|
target_ulong pc_start;
|
|
int num_insns;
|
|
uint16_t *gen_opc_end;
|
|
|
|
if (search_pc) {
|
|
qemu_log("search pc %d\n", search_pc);
|
|
}
|
|
|
|
num_insns = 0;
|
|
pc_start = tb->pc;
|
|
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
|
ctx.pc = pc_start;
|
|
ctx.saved_pc = -1;
|
|
ctx.tb = tb;
|
|
ctx.singlestep_enabled = cs->singlestep_enabled;
|
|
ctx.bstate = BS_NONE;
|
|
ctx.mem_idx = cpu_mmu_index(env);
|
|
|
|
tcg_clear_temp_count();
|
|
gen_tb_start();
|
|
while (ctx.bstate == BS_NONE) {
|
|
ctx.opcode = cpu_ldl_code(env, ctx.pc);
|
|
decode_opc(env, &ctx, 0);
|
|
|
|
num_insns++;
|
|
|
|
if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
|
|
break;
|
|
}
|
|
if (singlestep) {
|
|
break;
|
|
}
|
|
ctx.pc = ctx.next_pc;
|
|
}
|
|
|
|
gen_tb_end(tb, num_insns);
|
|
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
|
|
if (search_pc) {
|
|
printf("done_generating search pc\n");
|
|
} else {
|
|
tb->size = ctx.pc - pc_start;
|
|
tb->icount = num_insns;
|
|
}
|
|
if (tcg_check_temp_count()) {
|
|
printf("LEAK at %08x\n", env->PC);
|
|
}
|
|
|
|
#ifdef DEBUG_DISAS
|
|
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
|
log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
|
|
qemu_log("\n");
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
|
|
}
|
|
|
|
void
|
|
gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
|
|
}
|
|
|
|
void
|
|
restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
|
|
{
|
|
env->PC = tcg_ctx.gen_opc_pc[pc_pos];
|
|
}
|
|
/*
|
|
*
|
|
* Initialization
|
|
*
|
|
*/
|
|
|
|
void cpu_state_reset(CPUTriCoreState *env)
|
|
{
|
|
/* Reset Regs to Default Value */
|
|
env->PSW = 0xb80;
|
|
}
|
|
|
|
static void tricore_tcg_init_csfr(void)
|
|
{
|
|
cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PCXI), "PCXI");
|
|
cpu_PSW = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PSW), "PSW");
|
|
cpu_PC = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PC), "PC");
|
|
cpu_ICR = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, ICR), "ICR");
|
|
}
|
|
|
|
void tricore_tcg_init(void)
|
|
{
|
|
int i;
|
|
static int inited;
|
|
if (inited) {
|
|
return;
|
|
}
|
|
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
|
/* reg init */
|
|
for (i = 0 ; i < 16 ; i++) {
|
|
cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, gpr_a[i]),
|
|
regnames_a[i]);
|
|
}
|
|
for (i = 0 ; i < 16 ; i++) {
|
|
cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, gpr_d[i]),
|
|
regnames_d[i]);
|
|
}
|
|
tricore_tcg_init_csfr();
|
|
/* init PSW flag cache */
|
|
cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PSW_USB_C),
|
|
"PSW_C");
|
|
cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PSW_USB_V),
|
|
"PSW_V");
|
|
cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PSW_USB_SV),
|
|
"PSW_SV");
|
|
cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PSW_USB_AV),
|
|
"PSW_AV");
|
|
cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
|
|
offsetof(CPUTriCoreState, PSW_USB_SAV),
|
|
"PSW_SAV");
|
|
}
|