969 lines
30 KiB
C
969 lines
30 KiB
C
/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "sysemu/kvm.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "exec/log.h"
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enum {
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TLBRET_XI = -6,
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TLBRET_RI = -5,
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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};
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#if !defined(CONFIG_USER_ONLY)
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/* no MMU emulation */
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int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return TLBRET_MATCH;
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}
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/* fixed mapping MMU emulation */
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int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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if (address <= (int32_t)0x7FFFFFFFUL) {
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if (!(env->CP0_Status & (1 << CP0St_ERL)))
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*physical = address + 0x40000000UL;
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else
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*physical = address;
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} else if (address <= (int32_t)0xBFFFFFFFUL)
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*physical = address & 0x1FFFFFFF;
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else
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return TLBRET_MATCH;
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}
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/* MIPS32/MIPS64 R4000-style MMU emulation */
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int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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uint8_t ASID = env->CP0_EntryHi & 0xFF;
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int i;
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for (i = 0; i < env->tlb->tlb_in_use; i++) {
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r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
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/* 1k pages are not supported. */
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target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
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target_ulong tag = address & ~mask;
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target_ulong VPN = tlb->VPN & ~mask;
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#if defined(TARGET_MIPS64)
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tag &= env->SEGMask;
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#endif
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
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/* TLB match */
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int n = !!(address & mask & ~(mask >> 1));
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/* Check access rights */
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if (!(n ? tlb->V1 : tlb->V0)) {
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return TLBRET_INVALID;
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}
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if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
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return TLBRET_XI;
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}
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if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
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return TLBRET_RI;
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}
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if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
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*physical = tlb->PFN[n] | (address & (mask >> 1));
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*prot = PAGE_READ;
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if (n ? tlb->D1 : tlb->D0)
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*prot |= PAGE_WRITE;
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return TLBRET_MATCH;
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}
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return TLBRET_DIRTY;
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}
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}
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return TLBRET_NOMATCH;
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}
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static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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int *prot, target_ulong real_address,
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int rw, int access_type)
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{
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/* User mode can only access useg/xuseg */
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
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int kernel_mode = !user_mode && !supervisor_mode;
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#if defined(TARGET_MIPS64)
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
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#endif
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int ret = TLBRET_MATCH;
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/* effective address (modified for KVM T&E kernel segments) */
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target_ulong address = real_address;
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#define USEG_LIMIT 0x7FFFFFFFUL
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#define KSEG0_BASE 0x80000000UL
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#define KSEG1_BASE 0xA0000000UL
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#define KSEG2_BASE 0xC0000000UL
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#define KSEG3_BASE 0xE0000000UL
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#define KVM_KSEG0_BASE 0x40000000UL
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#define KVM_KSEG2_BASE 0x60000000UL
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if (kvm_enabled()) {
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/* KVM T&E adds guest kernel segments in useg */
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if (real_address >= KVM_KSEG0_BASE) {
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if (real_address < KVM_KSEG2_BASE) {
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/* kseg0 */
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address += KSEG0_BASE - KVM_KSEG0_BASE;
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} else if (real_address <= USEG_LIMIT) {
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/* kseg2/3 */
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address += KSEG2_BASE - KVM_KSEG2_BASE;
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}
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}
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}
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if (address <= USEG_LIMIT) {
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/* useg */
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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*physical = address & 0xFFFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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}
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#if defined(TARGET_MIPS64)
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} else if (address < 0x4000000000000000ULL) {
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/* xuseg */
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if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0x8000000000000000ULL) {
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/* xsseg */
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if ((supervisor_mode || kernel_mode) &&
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SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0xC000000000000000ULL) {
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/* xkphys */
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if (kernel_mode && KX &&
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(address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
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*physical = address & env->PAMask;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0xFFFFFFFF80000000ULL) {
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/* xkseg */
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if (kernel_mode && KX &&
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address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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#endif
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} else if (address < (int32_t)KSEG1_BASE) {
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/* kseg0 */
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if (kernel_mode) {
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*physical = address - (int32_t)KSEG0_BASE;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < (int32_t)KSEG2_BASE) {
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/* kseg1 */
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if (kernel_mode) {
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*physical = address - (int32_t)KSEG1_BASE;
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*prot = PAGE_READ | PAGE_WRITE;
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < (int32_t)KSEG3_BASE) {
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/* sseg (kseg2) */
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if (supervisor_mode || kernel_mode) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else {
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/* kseg3 */
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/* XXX: debug segment is not emulated */
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if (kernel_mode) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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}
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return ret;
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}
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void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
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{
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MIPSCPU *cpu = mips_env_get_cpu(env);
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/* Flush qemu's TLB and discard all shadowed entries. */
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tlb_flush(CPU(cpu), flush_global);
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env->tlb->tlb_in_use = env->tlb->nb_tlb;
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}
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/* Called for updates to CP0_Status. */
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & 0xff;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = env->CP0_Status_rw_bitmask;
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target_ulong old = env->CP0_Status;
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if (env->insn_flags & ISA_MIPS32R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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#if defined(TARGET_MIPS64)
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uint32_t ksux = (1 << CP0St_KX) & val;
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ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
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ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
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val = (val & ~(7 << CP0St_UX)) | ksux;
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#endif
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if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
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}
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env->CP0_Status = (old & ~mask) | (val & mask);
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#if defined(TARGET_MIPS64)
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if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
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/* Access to at least one of the 64-bit segments has been disabled */
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cpu_mips_tlb_flush(env, 1);
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}
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#endif
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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}
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = env->CP0_Cause;
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int i;
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if (env->insn_flags & ISA_MIPS32R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (env->insn_flags & ISA_MIPS32R6) {
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mask &= ~((1 << CP0Ca_WP) & val);
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}
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env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
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if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(env);
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} else {
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cpu_mips_start_count(env);
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}
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}
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/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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#endif
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static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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int rw, int tlb_error)
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{
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CPUState *cs = CPU(mips_env_get_cpu(env));
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int exception = 0, error_code = 0;
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if (rw == MMU_INST_FETCH) {
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error_code |= EXCP_INST_NOTAVAIL;
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}
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switch (tlb_error) {
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default:
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case TLBRET_BADADDR:
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/* Reference to kernel address from user mode or supervisor mode */
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/* Reference to supervisor address from user mode */
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if (rw == MMU_DATA_STORE) {
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exception = EXCP_AdES;
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} else {
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exception = EXCP_AdEL;
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}
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break;
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */
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if (rw == MMU_DATA_STORE) {
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exception = EXCP_TLBS;
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} else {
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exception = EXCP_TLBL;
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}
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error_code |= EXCP_TLB_NOMATCH;
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break;
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case TLBRET_INVALID:
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/* TLB match with no valid bit */
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if (rw == MMU_DATA_STORE) {
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exception = EXCP_TLBS;
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} else {
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exception = EXCP_TLBL;
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}
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break;
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case TLBRET_DIRTY:
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/* TLB match but 'D' bit is cleared */
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exception = EXCP_LTLBL;
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break;
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case TLBRET_XI:
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/* Execute-Inhibit Exception */
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if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
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exception = EXCP_TLBXI;
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} else {
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exception = EXCP_TLBL;
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}
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break;
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case TLBRET_RI:
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/* Read-Inhibit Exception */
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if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
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exception = EXCP_TLBRI;
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} else {
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exception = EXCP_TLBL;
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}
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break;
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}
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/* Raise exception */
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env->CP0_BadVAddr = address;
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env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
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((address >> 9) & 0x007ffff0);
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env->CP0_EntryHi =
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(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
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#if defined(TARGET_MIPS64)
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env->CP0_EntryHi &= env->SEGMask;
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env->CP0_XContext =
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/* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
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/* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
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/* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
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#endif
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cs->exception_index = exception;
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env->error_code = error_code;
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}
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#if !defined(CONFIG_USER_ONLY)
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hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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hwaddr phys_addr;
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int prot;
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if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
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ACCESS_INT) != 0) {
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return -1;
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}
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return phys_addr;
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}
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#endif
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int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
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int mmu_idx)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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#if !defined(CONFIG_USER_ONLY)
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hwaddr physical;
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int prot;
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int access_type;
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#endif
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int ret = 0;
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#if 0
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log_cpu_state(cs, 0);
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#endif
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qemu_log_mask(CPU_LOG_MMU,
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"%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, env->active_tc.PC, address, rw, mmu_idx);
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/* data access */
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#if !defined(CONFIG_USER_ONLY)
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/* XXX: put correct access by using cpu_restore_state()
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correctly */
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access_type = ACCESS_INT;
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ret = get_physical_address(env, &physical, &prot,
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address, rw, access_type);
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qemu_log_mask(CPU_LOG_MMU,
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"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
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" prot %d\n",
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__func__, address, ret, physical, prot);
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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ret = 0;
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} else if (ret < 0)
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#endif
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{
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raise_mmu_exception(env, address, rw, ret);
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ret = 1;
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}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
|
|
{
|
|
hwaddr physical;
|
|
int prot;
|
|
int access_type;
|
|
int ret = 0;
|
|
|
|
/* data access */
|
|
access_type = ACCESS_INT;
|
|
ret = get_physical_address(env, &physical, &prot,
|
|
address, rw, access_type);
|
|
if (ret != TLBRET_MATCH) {
|
|
raise_mmu_exception(env, address, rw, ret);
|
|
return -1LL;
|
|
} else {
|
|
return physical;
|
|
}
|
|
}
|
|
|
|
static const char * const excp_names[EXCP_LAST + 1] = {
|
|
[EXCP_RESET] = "reset",
|
|
[EXCP_SRESET] = "soft reset",
|
|
[EXCP_DSS] = "debug single step",
|
|
[EXCP_DINT] = "debug interrupt",
|
|
[EXCP_NMI] = "non-maskable interrupt",
|
|
[EXCP_MCHECK] = "machine check",
|
|
[EXCP_EXT_INTERRUPT] = "interrupt",
|
|
[EXCP_DFWATCH] = "deferred watchpoint",
|
|
[EXCP_DIB] = "debug instruction breakpoint",
|
|
[EXCP_IWATCH] = "instruction fetch watchpoint",
|
|
[EXCP_AdEL] = "address error load",
|
|
[EXCP_AdES] = "address error store",
|
|
[EXCP_TLBF] = "TLB refill",
|
|
[EXCP_IBE] = "instruction bus error",
|
|
[EXCP_DBp] = "debug breakpoint",
|
|
[EXCP_SYSCALL] = "syscall",
|
|
[EXCP_BREAK] = "break",
|
|
[EXCP_CpU] = "coprocessor unusable",
|
|
[EXCP_RI] = "reserved instruction",
|
|
[EXCP_OVERFLOW] = "arithmetic overflow",
|
|
[EXCP_TRAP] = "trap",
|
|
[EXCP_FPE] = "floating point",
|
|
[EXCP_DDBS] = "debug data break store",
|
|
[EXCP_DWATCH] = "data watchpoint",
|
|
[EXCP_LTLBL] = "TLB modify",
|
|
[EXCP_TLBL] = "TLB load",
|
|
[EXCP_TLBS] = "TLB store",
|
|
[EXCP_DBE] = "data bus error",
|
|
[EXCP_DDBL] = "debug data break load",
|
|
[EXCP_THREAD] = "thread",
|
|
[EXCP_MDMX] = "MDMX",
|
|
[EXCP_C2E] = "precise coprocessor 2",
|
|
[EXCP_CACHE] = "cache error",
|
|
[EXCP_TLBXI] = "TLB execute-inhibit",
|
|
[EXCP_TLBRI] = "TLB read-inhibit",
|
|
[EXCP_MSADIS] = "MSA disabled",
|
|
[EXCP_MSAFPE] = "MSA floating point",
|
|
};
|
|
#endif
|
|
|
|
target_ulong exception_resume_pc (CPUMIPSState *env)
|
|
{
|
|
target_ulong bad_pc;
|
|
target_ulong isa_mode;
|
|
|
|
isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
|
|
bad_pc = env->active_tc.PC | isa_mode;
|
|
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
/* If the exception was raised from a delay slot, come back to
|
|
the jump. */
|
|
bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
|
|
}
|
|
|
|
return bad_pc;
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
static void set_hflags_for_handler (CPUMIPSState *env)
|
|
{
|
|
/* Exception handlers are entered in 32-bit mode. */
|
|
env->hflags &= ~(MIPS_HFLAG_M16);
|
|
/* ...except that microMIPS lets you choose. */
|
|
if (env->insn_flags & ASE_MICROMIPS) {
|
|
env->hflags |= (!!(env->CP0_Config3
|
|
& (1 << CP0C3_ISA_ON_EXC))
|
|
<< MIPS_HFLAG_M16_SHIFT);
|
|
}
|
|
}
|
|
|
|
static inline void set_badinstr_registers(CPUMIPSState *env)
|
|
{
|
|
if (env->hflags & MIPS_HFLAG_M16) {
|
|
/* TODO: add BadInstr support for microMIPS */
|
|
return;
|
|
}
|
|
if (env->CP0_Config3 & (1 << CP0C3_BI)) {
|
|
env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
|
|
}
|
|
if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
|
|
(env->hflags & MIPS_HFLAG_BMASK)) {
|
|
env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void mips_cpu_do_interrupt(CPUState *cs)
|
|
{
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
MIPSCPU *cpu = MIPS_CPU(cs);
|
|
CPUMIPSState *env = &cpu->env;
|
|
bool update_badinstr = 0;
|
|
target_ulong offset;
|
|
int cause = -1;
|
|
const char *name;
|
|
|
|
if (qemu_loglevel_mask(CPU_LOG_INT)
|
|
&& cs->exception_index != EXCP_EXT_INTERRUPT) {
|
|
if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
|
|
name = "unknown";
|
|
} else {
|
|
name = excp_names[cs->exception_index];
|
|
}
|
|
|
|
qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
|
|
" %s exception\n",
|
|
__func__, env->active_tc.PC, env->CP0_EPC, name);
|
|
}
|
|
if (cs->exception_index == EXCP_EXT_INTERRUPT &&
|
|
(env->hflags & MIPS_HFLAG_DM)) {
|
|
cs->exception_index = EXCP_DINT;
|
|
}
|
|
offset = 0x180;
|
|
switch (cs->exception_index) {
|
|
case EXCP_DSS:
|
|
env->CP0_Debug |= 1 << CP0DB_DSS;
|
|
/* Debug single step cannot be raised inside a delay slot and
|
|
resume will always occur on the next instruction
|
|
(but we assume the pc has always been updated during
|
|
code translation). */
|
|
env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
|
|
goto enter_debug_mode;
|
|
case EXCP_DINT:
|
|
env->CP0_Debug |= 1 << CP0DB_DINT;
|
|
goto set_DEPC;
|
|
case EXCP_DIB:
|
|
env->CP0_Debug |= 1 << CP0DB_DIB;
|
|
goto set_DEPC;
|
|
case EXCP_DBp:
|
|
env->CP0_Debug |= 1 << CP0DB_DBp;
|
|
goto set_DEPC;
|
|
case EXCP_DDBS:
|
|
env->CP0_Debug |= 1 << CP0DB_DDBS;
|
|
goto set_DEPC;
|
|
case EXCP_DDBL:
|
|
env->CP0_Debug |= 1 << CP0DB_DDBL;
|
|
set_DEPC:
|
|
env->CP0_DEPC = exception_resume_pc(env);
|
|
env->hflags &= ~MIPS_HFLAG_BMASK;
|
|
enter_debug_mode:
|
|
if (env->insn_flags & ISA_MIPS3) {
|
|
env->hflags |= MIPS_HFLAG_64;
|
|
if (!(env->insn_flags & ISA_MIPS64R6) ||
|
|
env->CP0_Status & (1 << CP0St_KX)) {
|
|
env->hflags &= ~MIPS_HFLAG_AWRAP;
|
|
}
|
|
}
|
|
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
|
|
env->hflags &= ~(MIPS_HFLAG_KSU);
|
|
/* EJTAG probe trap enable is not implemented... */
|
|
if (!(env->CP0_Status & (1 << CP0St_EXL)))
|
|
env->CP0_Cause &= ~(1U << CP0Ca_BD);
|
|
env->active_tc.PC = (int32_t)0xBFC00480;
|
|
set_hflags_for_handler(env);
|
|
break;
|
|
case EXCP_RESET:
|
|
cpu_reset(CPU(cpu));
|
|
break;
|
|
case EXCP_SRESET:
|
|
env->CP0_Status |= (1 << CP0St_SR);
|
|
memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
|
|
goto set_error_EPC;
|
|
case EXCP_NMI:
|
|
env->CP0_Status |= (1 << CP0St_NMI);
|
|
set_error_EPC:
|
|
env->CP0_ErrorEPC = exception_resume_pc(env);
|
|
env->hflags &= ~MIPS_HFLAG_BMASK;
|
|
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
|
|
if (env->insn_flags & ISA_MIPS3) {
|
|
env->hflags |= MIPS_HFLAG_64;
|
|
if (!(env->insn_flags & ISA_MIPS64R6) ||
|
|
env->CP0_Status & (1 << CP0St_KX)) {
|
|
env->hflags &= ~MIPS_HFLAG_AWRAP;
|
|
}
|
|
}
|
|
env->hflags |= MIPS_HFLAG_CP0;
|
|
env->hflags &= ~(MIPS_HFLAG_KSU);
|
|
if (!(env->CP0_Status & (1 << CP0St_EXL)))
|
|
env->CP0_Cause &= ~(1U << CP0Ca_BD);
|
|
env->active_tc.PC = (int32_t)0xBFC00000;
|
|
set_hflags_for_handler(env);
|
|
break;
|
|
case EXCP_EXT_INTERRUPT:
|
|
cause = 0;
|
|
if (env->CP0_Cause & (1 << CP0Ca_IV)) {
|
|
uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
|
|
|
|
if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
|
|
offset = 0x200;
|
|
} else {
|
|
uint32_t vector = 0;
|
|
uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
|
|
|
|
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
|
|
/* For VEIC mode, the external interrupt controller feeds
|
|
* the vector through the CP0Cause IP lines. */
|
|
vector = pending;
|
|
} else {
|
|
/* Vectored Interrupts
|
|
* Mask with Status.IM7-IM0 to get enabled interrupts. */
|
|
pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
|
|
/* Find the highest-priority interrupt. */
|
|
while (pending >>= 1) {
|
|
vector++;
|
|
}
|
|
}
|
|
offset = 0x200 + (vector * (spacing << 5));
|
|
}
|
|
}
|
|
goto set_EPC;
|
|
case EXCP_LTLBL:
|
|
cause = 1;
|
|
update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
|
|
goto set_EPC;
|
|
case EXCP_TLBL:
|
|
cause = 2;
|
|
update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
|
|
if ((env->error_code & EXCP_TLB_NOMATCH) &&
|
|
!(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
#if defined(TARGET_MIPS64)
|
|
int R = env->CP0_BadVAddr >> 62;
|
|
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
|
|
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
|
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
|
|
|
if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
|
|
(!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
|
|
offset = 0x080;
|
|
else
|
|
#endif
|
|
offset = 0x000;
|
|
}
|
|
goto set_EPC;
|
|
case EXCP_TLBS:
|
|
cause = 3;
|
|
update_badinstr = 1;
|
|
if ((env->error_code & EXCP_TLB_NOMATCH) &&
|
|
!(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
#if defined(TARGET_MIPS64)
|
|
int R = env->CP0_BadVAddr >> 62;
|
|
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
|
|
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
|
|
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
|
|
|
|
if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
|
|
(!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
|
|
offset = 0x080;
|
|
else
|
|
#endif
|
|
offset = 0x000;
|
|
}
|
|
goto set_EPC;
|
|
case EXCP_AdEL:
|
|
cause = 4;
|
|
update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
|
|
goto set_EPC;
|
|
case EXCP_AdES:
|
|
cause = 5;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_IBE:
|
|
cause = 6;
|
|
goto set_EPC;
|
|
case EXCP_DBE:
|
|
cause = 7;
|
|
goto set_EPC;
|
|
case EXCP_SYSCALL:
|
|
cause = 8;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_BREAK:
|
|
cause = 9;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_RI:
|
|
cause = 10;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_CpU:
|
|
cause = 11;
|
|
update_badinstr = 1;
|
|
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
|
|
(env->error_code << CP0Ca_CE);
|
|
goto set_EPC;
|
|
case EXCP_OVERFLOW:
|
|
cause = 12;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_TRAP:
|
|
cause = 13;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_MSAFPE:
|
|
cause = 14;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_FPE:
|
|
cause = 15;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_C2E:
|
|
cause = 18;
|
|
goto set_EPC;
|
|
case EXCP_TLBRI:
|
|
cause = 19;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_TLBXI:
|
|
cause = 20;
|
|
goto set_EPC;
|
|
case EXCP_MSADIS:
|
|
cause = 21;
|
|
update_badinstr = 1;
|
|
goto set_EPC;
|
|
case EXCP_MDMX:
|
|
cause = 22;
|
|
goto set_EPC;
|
|
case EXCP_DWATCH:
|
|
cause = 23;
|
|
/* XXX: TODO: manage deferred watch exceptions */
|
|
goto set_EPC;
|
|
case EXCP_MCHECK:
|
|
cause = 24;
|
|
goto set_EPC;
|
|
case EXCP_THREAD:
|
|
cause = 25;
|
|
goto set_EPC;
|
|
case EXCP_DSPDIS:
|
|
cause = 26;
|
|
goto set_EPC;
|
|
case EXCP_CACHE:
|
|
cause = 30;
|
|
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
|
offset = 0x100;
|
|
} else {
|
|
offset = 0x20000100;
|
|
}
|
|
set_EPC:
|
|
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
|
|
env->CP0_EPC = exception_resume_pc(env);
|
|
if (update_badinstr) {
|
|
set_badinstr_registers(env);
|
|
}
|
|
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
env->CP0_Cause |= (1U << CP0Ca_BD);
|
|
} else {
|
|
env->CP0_Cause &= ~(1U << CP0Ca_BD);
|
|
}
|
|
env->CP0_Status |= (1 << CP0St_EXL);
|
|
if (env->insn_flags & ISA_MIPS3) {
|
|
env->hflags |= MIPS_HFLAG_64;
|
|
if (!(env->insn_flags & ISA_MIPS64R6) ||
|
|
env->CP0_Status & (1 << CP0St_KX)) {
|
|
env->hflags &= ~MIPS_HFLAG_AWRAP;
|
|
}
|
|
}
|
|
env->hflags |= MIPS_HFLAG_CP0;
|
|
env->hflags &= ~(MIPS_HFLAG_KSU);
|
|
}
|
|
env->hflags &= ~MIPS_HFLAG_BMASK;
|
|
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
|
env->active_tc.PC = (int32_t)0xBFC00200;
|
|
} else {
|
|
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
|
}
|
|
env->active_tc.PC += offset;
|
|
set_hflags_for_handler(env);
|
|
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
|
break;
|
|
default:
|
|
abort();
|
|
}
|
|
if (qemu_loglevel_mask(CPU_LOG_INT)
|
|
&& cs->exception_index != EXCP_EXT_INTERRUPT) {
|
|
qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
|
|
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
|
|
__func__, env->active_tc.PC, env->CP0_EPC, cause,
|
|
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
|
|
env->CP0_DEPC);
|
|
}
|
|
#endif
|
|
cs->exception_index = EXCP_NONE;
|
|
}
|
|
|
|
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
{
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
MIPSCPU *cpu = MIPS_CPU(cs);
|
|
CPUMIPSState *env = &cpu->env;
|
|
|
|
if (cpu_mips_hw_interrupts_enabled(env) &&
|
|
cpu_mips_hw_interrupts_pending(env)) {
|
|
/* Raise it */
|
|
cs->exception_index = EXCP_EXT_INTERRUPT;
|
|
env->error_code = 0;
|
|
mips_cpu_do_interrupt(cs);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
|
|
{
|
|
MIPSCPU *cpu = mips_env_get_cpu(env);
|
|
CPUState *cs;
|
|
r4k_tlb_t *tlb;
|
|
target_ulong addr;
|
|
target_ulong end;
|
|
uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
|
target_ulong mask;
|
|
|
|
tlb = &env->tlb->mmu.r4k.tlb[idx];
|
|
/* The qemu TLB is flushed when the ASID changes, so no need to
|
|
flush these entries again. */
|
|
if (tlb->G == 0 && tlb->ASID != ASID) {
|
|
return;
|
|
}
|
|
|
|
if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
|
|
/* For tlbwr, we can shadow the discarded entry into
|
|
a new (fake) TLB entry, as long as the guest can not
|
|
tell that it's there. */
|
|
env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
|
|
env->tlb->tlb_in_use++;
|
|
return;
|
|
}
|
|
|
|
/* 1k pages are not supported. */
|
|
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
|
if (tlb->V0) {
|
|
cs = CPU(cpu);
|
|
addr = tlb->VPN & ~mask;
|
|
#if defined(TARGET_MIPS64)
|
|
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
|
|
addr |= 0x3FFFFF0000000000ULL;
|
|
}
|
|
#endif
|
|
end = addr | (mask >> 1);
|
|
while (addr < end) {
|
|
tlb_flush_page(cs, addr);
|
|
addr += TARGET_PAGE_SIZE;
|
|
}
|
|
}
|
|
if (tlb->V1) {
|
|
cs = CPU(cpu);
|
|
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
|
|
#if defined(TARGET_MIPS64)
|
|
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
|
|
addr |= 0x3FFFFF0000000000ULL;
|
|
}
|
|
#endif
|
|
end = addr | mask;
|
|
while (addr - 1 < end) {
|
|
tlb_flush_page(cs, addr);
|
|
addr += TARGET_PAGE_SIZE;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
|
|
uint32_t exception,
|
|
int error_code,
|
|
uintptr_t pc)
|
|
{
|
|
CPUState *cs = CPU(mips_env_get_cpu(env));
|
|
|
|
if (exception < EXCP_SC) {
|
|
qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
|
|
__func__, exception, error_code);
|
|
}
|
|
cs->exception_index = exception;
|
|
env->error_code = error_code;
|
|
|
|
cpu_loop_exit_restore(cs, pc);
|
|
}
|