Xi Wang ff9f31d9a0 target/riscv: fix counter-enable checks in ctr() ... Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang <xi.wang@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-02-11 15:56:22 -08:00
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cpu_bits.h	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
cpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
cpu.h	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
csr.c	target/riscv: fix counter-enable checks in ctr()	2019-02-11 15:56:22 -08:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
helper.h
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
op_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
pmp.c	target/riscv/pmp.c: Fix pmp_decode_napot()	2018-12-20 12:26:39 -08:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	RISC-V: Add misa.MAFD checks to translate	2019-02-11 15:56:22 -08:00