qemu-e2k/target
Jose Martins 487a99551a target/riscv: fix VS interrupts forwarding to HS
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always considered enabled when
it should. The spec states that "Interrupts for higher-privilege modes,
y>x, are always globally enabled regardless of the setting of the global
yIE bit for the higher-privilege mode." and also "For purposes of
interrupt global enables, HS-mode is considered more privileged than
VS-mode, and VS-mode is considered more privileged than VU-mode". Also,
vs-level interrupts were not being taken into account unless V=1, but
should be unless delegated.

Finally, there is no need for a special case for to handle vs interrupts
as the current privilege level, the state of the global ie and of the
delegation registers should be enough to route all interrupts to the
appropriate privilege level in riscv_cpu_do_interrupt.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211026145126.11025-2-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-29 16:54:45 +10:00
..
alpha
arm target/arm: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
avr
cris
hexagon target/hexagon: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
hppa target/hppa: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
i386 target/i386: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
m68k target/m68k: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
microblaze target/microblaze: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
mips target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() 2021-10-18 00:41:36 +02:00
nios2 disas/nios2: Simplify endianess conversion 2021-10-22 18:07:30 +02:00
openrisc target/openrisc: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
ppc target/ppc: adding user read/write functions for PMCs 2021-10-21 11:42:47 +11:00
riscv target/riscv: fix VS interrupts forwarding to HS 2021-10-29 16:54:45 +10:00
rx target/rx: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
s390x target/s390x: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
sh4 target/sh4: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
sparc
tricore target/tricore: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
xtensa target/xtensa: Drop check for singlestep_enabled 2021-10-15 16:39:15 -07:00
Kconfig
meson.build