babc1f3009
Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20171126231634.9531-14-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/*
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* Xilinx Zynq MPSoC emulation
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*
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* Copyright (C) 2015 Xilinx Inc
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef XLNX_ZYNQMP_H
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#include "qemu-common.h"
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#include "hw/arm/arm.h"
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#include "hw/intc/arm_gic.h"
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#include "hw/net/cadence_gem.h"
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#include "hw/char/cadence_uart.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "hw/sd/sdhci.h"
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#include "hw/ssi/xilinx_spips.h"
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#include "hw/dma/xlnx_dpdma.h"
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#include "hw/display/xlnx_dp.h"
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#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
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#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
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TYPE_XLNX_ZYNQMP)
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#define XLNX_ZYNQMP_NUM_APU_CPUS 4
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#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
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#define XLNX_ZYNQMP_NUM_GEMS 4
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#define XLNX_ZYNQMP_NUM_UARTS 2
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#define XLNX_ZYNQMP_NUM_SDHCI 2
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#define XLNX_ZYNQMP_NUM_SPIS 2
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#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
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#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
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#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
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#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
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#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
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#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
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#define XLNX_ZYNQMP_GIC_REGIONS 2
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/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
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* and under-decodes the 64k region. This mirrors the 4k regions to every 4k
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* aligned address in the 64k region. To implement each GIC region needs a
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* number of memory region aliases.
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*/
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#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
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#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
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#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
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#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull
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#define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull
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#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
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XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
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typedef struct XlnxZynqMPState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
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ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
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GICState gic;
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MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
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MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
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MemoryRegion *ddr_ram;
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MemoryRegion ddr_ram_low, ddr_ram_high;
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CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
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CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
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SysbusAHCIState sata;
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SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
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XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
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XlnxZynqMPQSPIPS qspi;
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XlnxDPState dp;
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XlnxDPDMAState dpdma;
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char *boot_cpu;
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ARMCPU *boot_cpu_ptr;
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/* Has the ARM Security extensions? */
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bool secure;
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/* Has the ARM Virtualization extensions? */
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bool virt;
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/* Has the RPU subsystem? */
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bool has_rpu;
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} XlnxZynqMPState;
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#define XLNX_ZYNQMP_H
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#endif
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